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PDF SN74LS168 Data sheet ( Hoja de datos )

Número de pieza SN74LS168
Descripción BCD DECADE 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS
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SN74LS168
BCD DECADE
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL
COUNTERS
The SN54 / 74LS168 is a fully synchronous 4-stage up/down
counter featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U / D input to control the
direction of counting. The SN54/ 74LS168 counts in a BCD decade (8,
4, 2, 1) sequence. All state changes, whether in counting or parallel
loading, are initiated by the LOW-to-HIGH transition of the clock.
• Low Power Dissipation 100 mW Typical
• High-Speed Count Frequency 30 MHz Typical
• Fully Synchronous Operation
• Full Carry Lookahead for Easy Cascading
• Single Up / Down Control Input
• Positive Edge-Trigger Operation
• Input Clamp Diodes Limit High-Speed Termination Effects
http://onsemi.com
BCD DECADE
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as the Dual
In-Line Package.
123
4 56
78
U/D CP P0 P1 P2 P3 CEP GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CEP
CET
CP
PE
U/D
P0−P3
Q0−Q3
TC
Count Enable Parallel (Active LOW) Input
Count Enable Trickle (Active LOW) Input
Clock Pulse (Active positive going edge) Input
Parallel Enable (Active LOW) Input
Up-Down Count Control Input
Parallel Data Inputs
Flip-Flop Outputs
Terminal Count (Active LOW) Output
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
93 4 5 6
1
PE
U/D
P0
P1
P2
P3
7 CEP
10 CET
TC 15
2 CP
Q0 Q1 Q2 Q3
14 13 12 11
VCC = PIN 16
GND = PIN 8
Publication Order Number:
SN74LS168/D

1 page




SN74LS168 pdf
SN74LS168
CP 1.3 V
Q OR TC
AC WAVEFORMS
1/fmax
tW
1.3 V
tPHL
1.3 V
tPLH
1.3 V
1.3 V
CET
TC
1.3 V
tPLH
1.3 V
1.3 V
tPHL
1.3 V
Figure 1. Clock to Output Delays,
Count Frequency, and Clock Pulse Width
Figure 2. Count Enable Trickle Input
To Terminal Count Output Delays
CP 1.3 V 1.3 V 1.3 V
tPLH
TC 1.3 V
tPHL
1.3 V
Figure 3. Clock to Terminal Delays
CP
ts(H)
P0 • P1 • P2 • P3 1.3 V
1.3 V
th(H) = 0 ts(L)
1.3 V 1.3 V
1.3 V
th(L) = 0
1.3 V
Q0 • Q1 • Q2 • Q3
Figure 4. Setup Time (ts) and Hold (th)
for Parallel Data Inputs
CP
ts(L)
SR OR PE 1.3 V
1.3 V
th(L) = 0
1.3 V
ts(H)
1.3 V
1.3 V
th(H) = 0
1.3 V
CP
ts(H)
CEP 1.3 V
ts(H)
CET 1.3 V
1.3 V
th(H) = 0 ts(L)
1.3 V 1.3 V
th(H) = 0
1.3 V
1.3 V
th(L) = 0
1.3 V
ts(L)
1.3 V
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
1.3 V
th(L) = 0
1.3 V
Figure 5. Setup Time and Hold Time for
Count Enable and Parallel Enable Inputs,
and Up-Down Control Inputs
U/D
tPLH
TC
1.3 V
1.3 V
1.3 V
tPHL
1.3 V
Figure 6. Up-Down Input to
Terminal Count Output Delays
http://onsemi.com
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