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PDF A25L512A Data sheet ( Hoja de datos )
| Número de pieza | A25L512A | |
| Descripción | Serial Flash Memory | |
| Fabricantes | AMIC | |
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A25L512A Series
512Kbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
512Kbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Revision History
Rev. No.
0.0
0.1
1.0
1.1
1.2
1.3
1.4
History
Initial issue
Remove –U grade
Final version release
P6:Add small sector protect function
Add automotive grade (-AF)
Change 8-pin USON(2*3mm) package outline dimensions
Add “AEC-Q100 Grade 3 Certification” in FEATURES
Modify 8-pin USON(2*3mm) package outline dimensions
Issue Date
September 11, 2012
October 11, 2012
October 15, 2012
January 11, 2013
March 6, 2014
August 1, 2014
November 14, 2014
Remark
Preliminary
Final
(November, 2014, Version 1.4)
AMIC Technology Corp.
1 page  
SPI MODES
These devices can be driven by a microcontroller with its SPI
peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edge of Serial Clock (C), and output data is available from the
A25L512A Series
falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2,
is the clock polarity when the bus master is in Stand-by mode
and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)Æ Mode 0
– C remains at 1 for (CPOL=1, CPHA=1)Æ Mode 3
Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA)
= (0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
(ST6, ST7, ST9,
ST10, Other)
CS3 CS2 CS1
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
C DO DIO
SPI Memory
Device
S W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
Mode 0 0
0C
Mode 3 1
1C
DIO
DO
MSB
MSB
(November, 2014, Version 1.4)
4 AMIC Technology Corp.
5 Page 
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the
Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every
Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and
Write Status Register (WRSR) instruction.
A25L512A Series
The Write Enable (WREN) instruction is entered by driving
Chip Select ( S ) Low, sending the instruction code, and then
driving Chip Select ( S ) High.
Figure 4. Write Enable (WREN) Instruction Sequence
S
01 23 45 67
C
Instruction
DIO
High Impedance
DO
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5.) resets the
Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip
Select ( S ) Low, sending the instruction code, and then driving
Chip The Write Enable Latch (WEL) bit is reset under the
following conditions:
﹣ Power-up
﹣ Write Disable (WRDI) instruction completion
﹣ Write Status Register (WRSR) instruction completion
﹣ Page Program (PP) instruction completion
﹣ Sector Erase (SE) instruction completion
﹣ Bulk Erase (BE) instruction completion
Figure 5. Write Disable (WRDI) Instruction Sequence
S
01 23 45 67
C
Instruction
DIO
High Impedance
DO
(November, 2014, Version 1.4)
10 AMIC Technology Corp.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A25L512A.PDF ] | |
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