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PDF MTB50N06V Data sheet ( Hoja de datos )
| Número de pieza | MTB50N06V | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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MTB50N06V
Preferred Device
Power MOSFET
42 Amps, 60 Volts
N−Channel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1.0 MΩ)
Gate−Source Voltage
− Continuous
− Non−Repetitive (tp ≤ 10 ms)
Drain Current − Continuous @ 25°C
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C
(Note 1)
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60 Vdc
60 Vdc
± 20
± 25
42
30
147
125
0.83
3.0
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
Operating and Storage Temperature
Range
TJ, Tstg
− 55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 42 Apk, L = 0.454 μH, RG = 25 Ω)
EAS
400 mJ
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
RθJC
RθJA
RθJA
°C/W
1.2
62.5
50
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
TL
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
42 AMPERES
60 VOLTS
RDS(on) = 28 mΩ
N−Channel
D
G
12
3
S
4
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
MTB50N06V
AYWW
12
Gate Drain
3
Source
A = Assembly Location
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MTB50N06V
MTB50N06VT4
D2PAK
D2PAK
50 Units/Rail
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 5
1
Publication Order Number:
MTB50N06V/D
1 page  
MTB50N06V
14
12
10
8
Q1
6
4
QT
Q2
56
48
40
VGS
32
ID = 42 A
TJ = 25°C
24
16
1000
VDD = 25 V
ID = 42 A
VGS = 10 V
TJ = 25°C
100
tr
tf
td(off)
10 td(on)
28
Q3
0
VDS
0 10 20 30 40
QT, TOTAL CHARGE (nC)
0
50
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1
1 10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
50
VGS = 0 V
40 TJ = 25°C
100
30
20
10
0
0.5 0.6 0.7 0.8 0.9 1 1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
5
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| PDF Descargar | [ Datasheet MTB50N06V.PDF ] | |
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