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PDF AS1860 Data sheet ( Hoja de datos )
| Número de pieza | AS1860 | |
| Descripción | 60W/90W PoE PD Controllers | |
| Fabricantes | Akros Silicon | |
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AS1860 — 60W/90W PoE PD Controllers with HV Isolation
and Quad DC-DC Outputs
GENERAL DESCRIPTION
The AS1860 integrates Akros GreenEdge™ Isolation technology
with next generation Power-over-Ethernet (PoE) PD and integrated
isolated high speed digital communication to deliver up to 90W to an
isolated secondary side comprising of four independent outputs.
Delivering 90W enables a new range of PoE PD capabilities and
solutions which greatly expands the markets for PoE.
The AS1860’s 90W capability is fully backwards compatible with
Type 1 (IEEE® 802.3af) and Type 2 (IEEE® 802.3at) compliant PD.
This is integrated with high-voltage isolation and quad-output digital
power DC-DC converters – resulting in a complete PoE & Power
management solution in a single device with minimal external
components.
In addition to enabling digital PoE power conversion, Akros
GreenEdge™ isolation enables direct digital management of both
isolated Primary power and Secondary system power for real time
end-to-end Green Power application capabilities.
TYPICAL APPLICATIONS
Voice-over-IP (VoIP) phones
Wireless LAN & WiMAX access points (WAP)
Pan, Tilt, Zoom (PTZ) Cameras, IP cameras
Thin-client and notebook computers
Fiber-to-the-home (FTTH) terminals
Point-of-sale (PoS) terminals, RFID readers
FEATURES
PoE PD Controller
Fully Integrated 60/90W PD controller
Backwards compatible with Type 1 and Type 2 IEEE®
802.3af/at Compliant PD
60/90W power up can be controlled by PSE or AS1860
AS1860 will control safe 60/90W delivery from “Dumb” sources
4-pair power detection & secondary side logic notification
Automatic Type 1, Type2 & 60W PoE detection in HW & I2C
Modes
Low Resistance PD Power FET Switch (0.5 typical)
Primary‐Side DC‐DC Controller
High-efficiency DC-DC Controller with Digital Optimization
Primary-Secondary High-voltage integrated Digital Isolation
Programmable Primary Clock Frequency
Local-power operation down to 9.5V
Secondary‐Side Power Outputs
Programmable PWM Frequencies synched to External Clock
Output #1: Sync Controller with programmable power-FET
timing for high efficiency at both light and full load
Outputs #2 & #3: Buck Regulators w/2A FETs
Output #4: DC-DC Controller for Buck, Boost, or LED Boost
platform applications
Power Management
Hardware programmable start-up power sequencing
Primary-side power monitoring & control from Secondary-side
Individual output Power-Good management
Voltage margining for each output
Primary GPIO/ADC controlled via Secondary GPIO or I2C
5V µC-compatible with interrupt on alarm services
Programmable watchdog timer
SIMPLIFIED APPLICATION DIAGRAM
EMC Compliance and Protection
Slew-rate-controlled power drivers
Multi-phased PWM clocking, with External Sync clock option
Optional spread-spectrum clocking available for all PWMs
Over-current, Under/Over-voltage and Short-circuit Protection
High-temperature warning and shutdown
Meets IEC 61000-4-2/3/4/5/6, IEC60747, IEC 60950, DIN
EN60747-5-2 (VDE0884), & UL1577 requirements for EMC
compliance and basic isolation to 2120 VDC (1500 VRMS)
100V Process for PoE transient voltage robustness
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 www.AkrosSilicon.com
1 page  
AS1860
TABLES
Table 1 - AS1860 Signal Descriptions - Primary Side .......................................................................................................................... 6
Table 2 - AS1860 Signal Descriptions - Secondary Side...................................................................................................................... 8
Table 3 - Absolute Maximum Ratings................................................................................................................................................. 11
Table 4 - Normal Operating Conditions .............................................................................................................................................. 11
Table 5 - PD Section Electrical Characteristics .................................................................................................................................. 11
Table 6 - Primary Side Digital, I/O, and A/D Electrical Characteristics ............................................................................................... 12
Table 7 - Primary Side DC-DC Controller Electrical Characteristics................................................................................................... 13
Table 8 - Secondary Side Sync Controller (Output #1) Electrical Characteristics............................................................................... 13
Table 9 - Secondary Side DC-DC Regulators (Outputs #2, #3) Electrical Characteristics ................................................................. 14
Table 10 - Secondary Side DC-DC Controller (Output #4) Electrical Characteristics ......................................................................... 14
Table 11 - Secondary Side Digital I/O and I2C Electrical Characteristics ........................................................................................... 16
Table 12 - Thermal Protection Electrical Characteristics .................................................................................................................... 17
Table 13 - Isolation Electrical Characteristics ..................................................................................................................................... 17
Table 14 - Classification Map ............................................................................................................................................................. 21
Table 15 - AT_DET and LDET Operation ........................................................................................................................................... 22
Table 16 - Typical LDET External Resistor Design............................................................................................................................. 22
Table 17 - PWM Clock Rate Configuration ......................................................................................................................................... 23
Table 18 - Sync & Overlap Delay Timing Limit ................................................................................................................................... 24
Table 19 - SYNC_DLY & SYNC_OVL Resistor Calculation Example ................................................................................................ 24
Table 20 - AS1860 Device Address Configuration ............................................................................................................................. 33
Table 21 - AS1860 Register Address Word........................................................................................................................................ 34
Table 22 - AS1860 Register and Bit Summary ................................................................................................................................... 35
Table 23 - Alarms and Power Status (Read-Only) - 00h .................................................................................................................... 36
Table 24 - Interrupt Mask (R/W) - 01h ................................................................................................................................................ 36
Table 25 - Interrupt Status (Read-Only) - 02h .................................................................................................................................... 37
Table 26 - PGOOD Voltage Masks (R/W) - 03h ................................................................................................................................. 37
Table 27 - Watchdog Enable, Mask, Service (R/W) - 04h .................................................................................................................. 38
Table 28 - PGOOD & Watchdog History (R/W) - 05h ......................................................................................................................... 38
Table 29 - Device Control and I/O Status (R/W) - 06h........................................................................................................................ 39
Table 30 - Watchdog Timeout (R/W) - 07h ......................................................................................................................................... 39
Table 31 - ADCIN Voltage (Read-Only) - 08h..................................................................................................................................... 39
Table 32 - ADCIN Alarm Threshold (R/W) - 09h................................................................................................................................. 39
Table 33 - PD Status and System Clock Control (R/W) - 0Ah ............................................................................................................ 39
Table 34 - PD Voltage (Read-Only) - 0Bh .......................................................................................................................................... 40
Table 35 - PD Current (Read-Only) - 0Ch .......................................................................................................................................... 40
Table 36 - PD Over-Current Alarm Threshold (R/W) - 0Dh ................................................................................................................ 40
Table 37 - Outputs 1, 2 Disable & Margin Control (R/W) - 0Eh .......................................................................................................... 41
Table 38 - Outputs 3, 4 Disable & Margin Control (R/W) - 0Fh .......................................................................................................... 41
Table 39 - PoE Design Framework Summary .................................................................................................................................... 42
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 http://www.AkrosSilicon.com
5
5 Page 
AS1860
TEST SPECIFICATIONS
Table 3 - Absolute Maximum Ratings
Parameter
48VIN, 48N, RSIG: to 48RTN
48VIN: to 48N
48VIN, 48N, RSIG: to 48RTN (under steady-state conditions)
48VIN: to 48N (under steady-state conditions)
GATE, VBIAS, VBP: to 48N
LDET: to 48VIN
RCLASS, CLIM, RB, VDD5I: to 48RTN
ADCIN to 48RTN
VDD3V_OUT, VDD3V_IN: to 48N
Max
100 1
100 1
60 2
60 2
20
no more than 6V less
than 48VIN
6
4
4
Unit
V
V
V
V
V
V
V
V
V
ISENSEP, CSS, SYNC_DLY, SYNC_OVL, MODE, GPIP, GPOP, PRI_DIV,
I2C_ADR, SEC_DIV, WD_MODE: to 48N
VBOOST: to SGND
VP, LX2, LX3, LX4, LX4_SENSE, FB1, FB2, FB3, FB4: to SGND
CLK_IN, ISENSES, SEC_EN, COMP1, AGND1, PGOOD, VDD3V_ISEC,
VDD3V_OSEC: to SGND
VDD_SYNC, SYNC_OUT, INTB/AT_DET, SCL/GPIS, SDIO/GPOS, WDOG:
to SGND
AGND2, AGND3, AGND4, COMP4, ISENP4, ISENN4, LSD4, HSD4, EN2,
EN3, EN4, BUCK_EN: to SGND
ESD Rating, Human body model (per JESD22-A114)
ESD charged device model
ESD machine model
ESD System level (contact/air) at RJ-45 (per IEC61000-4-2)
Storage Temperature
Operating Junction Temperature
4
12
6
4
6
6
2
500
200
8/15
165
125
V
V
V
V
V
V
kV
V
V
kV
°C
°C
1 The AS1860 has a fast internal surge clamp for transient conditions such as system startup and other noise conditions; the device must not be
exposed to sustained over-voltage condition at this level.
2 Under steady state conditions; higher voltage level is acceptable under transient conditions.
Unless otherwise noted all Test Specifications apply over the full -40°C to 85°C operating temperature range.
CAUTION: Exceeding the maximum ratings specified in this table may cause permanent damage to the device.
Table 4 - Normal Operating Conditions
Parameter
VIN_AF
VIN_AT
VAUX (optional local power)
Thermal Resistance, Junction to Case, θJC
Thermal Resistance, Junction to Ambient, θJA
Operating temperature range
Min
37
42.5
9.5
-40
Typ1
48
48
5
20
Max Unit Conditions
57 V Measured at the Network Interface
57 V Measured at the Network Interface
57 V Measured at 48VIN for full VLDET
range (referenced to 48N)
°C/W Operating Junction Temperature
125°C, max
°C/W Operating Junction Temperature
125°C, max
85 °C
1 Typical specifications not 100% tested. Performance guaranteed by design and/or other correlation methods.
Table 5 - PD Section Electrical Characteristics
Symbol
Parameter
IINRUSH_AF Inrush current limit - AF PD
IINRUSH_AT Inrush current limit - AT PD
ILIM_AF
PoE current limit - AF PD
ILIM_AT
PoE current limit - AT PD
Min
350
720
Typ1
120
240
400
750
Max
500
1000
Unit Conditions2
mA 13W
mA 30W
mA 13W, CLIM = 48RTN
mA 30W, CLIM = VDD5I
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000 http://www.AkrosSilicon.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS1860.PDF ] | |
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