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ON Semiconductor - 3.3 V ECL Programmable Delay Chip

Numéro de référence MC100EP196A
Description 3.3 V ECL Programmable Delay Chip
Fabricant ON Semiconductor 
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MC100EP196A fiche technique
MC100EP196A
3.3 V ECL Programmable
Delay Chip With FTUNE
The MC100EP196A is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides
variable delay of a differential NECL/PECL input transition. It has
similar architecture to the EP195 with the added feature of further
tunability in delay using the FTUNE pin. The FTUNE input takes an
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analog voltage from VCC to VEE to fine tune the output delay from
0 to 60 ps.
MARKING
The delay section consists of a programmable matrix of gates and
DIAGRAM*
multiplexers as shown in the logic diagram, Figure 2. The delay
increment of the EP196A has a digitally selectable resolution of about
1
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
1 32
QFN32
MN SUFFIX
CASE 488AM
MC100
EP196A
ALYWG
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
A = Assembly Location
Table 6 and Figure 3.
The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level
signals. Because the MC100EP196A is designed using a chain of
multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
D10 is provided for controlling Pins 14 and 15, CASCADE and
CASCADE, also latched by LEN, in cascading multiple PDCs for
*For additional marking information, refer to
Application Note AND8002/D.
increased programmable range. The cascade logic allows full control of
multiple PDCs. Switching devices from all “1” states on D[0:9] with
SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will
increase the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
combinations of interconnects between VEF (pin 7) and VCF (pin 8) for
receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and VEF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to VCF and leave open VEF pin. The 1.5 V reference voltage at
the VCF pin can be accomplished by placing a 2.2 kW resistor between
VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Maximum Input Clock Frequency >1.2 GHz Typical
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
Programmable Range: 0 ns to 10 ns
A Logic High on the EN Pin Will Force Q to Logic Low
Delay Range: 2.2 ns to 12.4 ns
D[10:0] Can Select Either LVPECL, LVCMOS, or
10 ps Increments
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
LVTTL Input Levels
VBB Output Reference Voltage
Pb−Free Packages are Available*
VCC = 0 V with VEE = −3.0 V to −3.6 V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
September, 2006 − Rev. 0
1
Publication Order Number:
MC100EP196A/D

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