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PDF NB3N65027 Data sheet ( Hoja de datos )
| Número de pieza | NB3N65027 | |
| Descripción | 3.3V Programmable 3-PLL Clock Synthesizer | |
| Fabricantes | ON Semiconductor | |
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NB3N65027
3.3V Programmable 3-PLL Clock
Synthesizer with
6 LVTTL/LVCMOS Outputs w/OE
The NB3N65027 is a LVCMOS PLL−synthesized clock generator.
It accepts a 10 MHz to 27 MHz clock or fundamental mode crystal as
the reference source and drives three independent, low noise
phase−locked loops (PLLs).
Control lines ACSx, BCSx and CCS will select their appropriate
bank output frequencies. ACS1 and BCS1 are two−level
LVTTL/LVCMOS inputs, High and Low. ACS0, BCS0 and CCS are
three−level LVCMOS inputs, High, Mid and Low.
The NB3N65027 has three independent LVTTL/LVCMOS output
banks of two outputs each. Banks A and B offer a 1X and a 1/2X
output. Using a 25 MHz crystal, the selectable output frequencies
range from 16 2/3 MHz to 133 1/3 MHz. A 12.5 MHz crystal offers
from 8 1/3 MHz to 66 2/3 MHz. In addition, the NB3N65027 will
generate a buffered reference LVTTL/LVCMOS output, REFOUT,
10 MHz to 27 MHz. See Tables 2 through 9 for the variety of available
output frequencies. The OE pin, when set LOW, will disable the output
drivers to high impedance.
The NB3N65027 operates from a single +3.3 V supply across the
operating temperature range from −40°C to +85°C, and is offered in a
QSOP−20 RoHS compliant package.
The NB3N65027 provides the optimum combination of low cost,
flexibility, and high performance for Network, PCI and SDRAM
applications.
Features
http://onsemi.com
MARKING DIAGRAM
3N65027
AWLYWWG
QSOP20
CASE 492AC
3N65027 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
• 12.5 MHz or 25 MHz Fundamental Crystal or Clock
Input
• Six Output Clocks with Selectable Frequencies
• Buffered Crystal Reference Output
• SDRAM Frequencies of 67, 83, 100, and 133 MHz
• Operating Range: VCC = 3.3 V ±10%
• QSOP−20 Package, 150 mil
• −40°C to +85°C Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
• LVCMOS with 25 mA Output Drive Capability at TTL
Levels
VDD
ACS1
ACS0
BCS1
BCS0
CCS
25 or 12.5 MHz
crystal or clock
X1/ICLK
X2 CLX2
PLLA
PLLB
PLLC
Buffer /
Oscillator
Clock
Synthesis
and Control
Circuitry
CLX1
GND
Figure 1. Simplified Logic Diagram
CLKA1
B2 CLKA2
CLKB1
B2 CLKB2
CLKC1
CLKC2
REFOUT
OE (all outputs)
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 2
1
Publication Order Number:
NB3N65027/D
1 page  
NB3N65027
Table 12. DC CHARACTERISTICS VDD = 3.3V $10%, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min Typ Max Unit
POWER SUPPLY
VDD Power Supply Voltage; GND = 0 V
IDD Power Supply Current for VDD (Inputs and Outputs Open)
OUTPUTS
3.0 3.3 3.6 V
40 60 mA
VOH Output HIGH Voltage; VDD = 3.3V
IOH = −25 mA
2.4
IOH = −8mA VDD – 0.4
V
VOL Output LOW Voltage;
IOS Output Short Circuit Current, Each Output
X1/CLK INPUT PIN, ONLY
IOL = 25 mA
0.8 V
±50 mA
VIH Input HIGH Voltage
VIL Input LOW Voltage
TRI−LEVEL TYPE INPUTS: ACS0, BCS0, CCS
VDD / 2 + 1
VDD / 2 − 1
V
V
VIH Input HIGH Voltage
VIL Input LOW Voltage
TWO−LEVEL TYPE INPUTS: ACS1, BCS1, OE
VDD – 0.5
V
0.5 V
VIH Input HIGH Voltage
VIL Input LOW Voltage
2.0 V
0.8 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 13. AC CHARACTERISTICS VDD = 3.3V $10%, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
fIN Input Frequency, Crystal or Clock
tDC Output Clock Duty Cycle at VDD/2, 15 pF Load
Frequency Error, all clocks, 15 pF Load
10
40
tor,, tof
Output Rise/Fall Times; 0.8 V to 2.0 V, 15 pF Load
Absolute Jitter, short−term; variation from mean, 15 pF Load
Typ
12.5 or 25
50
$120
Max
27
60
0
1.5
Unit
MHz
%
ppm
ns
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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