NB3U1548C Datasheet PDF - ON Semiconductor
| Part Number | NB3U1548C | |
| Description | 3.3V/2.5V/1.8V/1.5V 160MHz 1:4 LVCMOS/LVTTL Low Skew Over Voltage Tolerant Fanout Buffer | |
| Manufacturers | ON Semiconductor | |
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NB3U1548C
3.3V/2.5V/1.8V/1.5V 160 MHz
1:4 LVCMOS/LVTTL Low
Skew Over Voltage Tolerant
Fanout Buffer
Description
The NB3U1548C is an LVCMOS, overvoltage tolerant clock fanout
buffer targeted for clock generation in high performance
telecommunication, networking and computing applications. The
device is optimized for low skew clock distribution in low voltage
applications. The input overvoltage tolerance enables using this
device in mixed mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance state.
Guaranteed output skew characteristics make the NB3U1548C ideal
for those applications demanding well defined performance and
repeatability. The NB3U1548C is packaged in a small SOIC−8 and in
an TSSOP−8 package.
Features
• Low skew 1:4 Fanout Buffer
• Supports 3.3 V, 2.5 V, 1.8 V and 1.5 V Power Supplies
• LVCMOS Input and Output Levels
• 3.6 V Overvoltage Tolerance at the Clock and Control Inputs
• Supports Clock Frequencies up to 160 MHz
• LVCMOS Compatible Control Input for Output Disable
• Output Disabled to a High Impedance State
• −40°C to 85°C Ambient Operating Temperature
• Available in Pb−Free RoHS Compliant Packages (SOIC−8,
TSSOP−8)
• These Devices are Pb−Free and are RoHS Compliant
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948S
MARKING
DIAGRAMS
8
1548C
ALYWG
G
1
8
154
YWW
AG
1
A = Assembly Location
L = Wafer Lot
Y = Year
W, WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 3
1
Publication Order Number:
NB3U1548C/D
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NB3U1548C
Table 6. AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min Typ Max Units
AC CHARACTERISTICS, VDD = 3.3 V + 5%, TA = −405C to 855C
fOUT
tpLH
Output Frequency
Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
0.7 2.1 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
0.7 2.1 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time, (active to high−impedance)
Enable Time, (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5 MHz
0.094
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
0.33
48
1.2 ns
53 %
AC CHARACTERISTICS, VDD = 2.5 V + 5%, TA = −405C to 855C
fOUT
Output Frequency
tpLH Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
0.8 2.0 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
0.8 2.0 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5 MHz
0.076
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
0.33
45
1.2 ns
53 %
AC CHARACTERISTICS, VDD = 1.8 V + 0.15 V, TA = −405C to 855C
fOUT
Output Frequency
tpLH Propagation Delay
(low to high transition); (Notes 4, 8)
160 MHz
1.1 2.8 ns
tpHL Propagation Delay
(high to low transition); (Notes 4, 8)
1.1 2.8 ns
tPLZ, tPHZ
tPZL, tPZH
tsk(o)
Disable Time (active to high−impedance)
Enable Time (high−impedance to active)
Output Skew; (Notes 5, 6)
10 ns
10 ns
250 ps
tsk(pp)
Part−to−Part Skew; (Notes 5, 7)
800 ps
tjit
Buffer Additive Phase Jitter, RMS
25 MHz, Integration Range:
12 kHz − 5MHz
0.193
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Characterized up to FOUT ≤ 150 MHz.
4. Measured from the VDD/2 of the input to VDD/2 of the output.
5. This parameter is defined in accordance with JEDEC Standard 65.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
7. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
8. With rail to rail input clock.
www.onsemi.com
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| Information | Total 11 Pages | |
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