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PDF MC74HC597A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC597A | |
| Descripción | 8-Bit Serial or ParallelInput/Serial-Output Shift Register | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HC597A
8-Bit Serial or Parallel-
Input/Serial-Output Shift
Register with Input Latch
High−Performance Silicon−Gate CMOS
The MC74HC597A is identical in pinout to the LS597. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of an 8−bit input latch which feeds parallel data
to an 8−bit shift register. Data can also be loaded serially.
The HC597A is similar in function to the HC589A, which is a
3−state device.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 516 FETs or 129 Equivalent Gates
• These are Pb−Free Devices*
http://onsemi.com
16
1
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
HC597AG
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
HC
597A
ALYWG
G
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 3
1
Publication Order Number:
MC74HC597A/D
1 page  
MC74HC597A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
fmax
Parameter
Maximum Clock Frequency (50% Duty Cycle), Shift Clock
(Figures 4 and 10)
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QH
(Figures 3 and 10)
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to QH
(Figures 4 and 10)
tPHL Maximum Propagation Delay, Reset to QH
(Figures 5 and 10)
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH
(Figures 6 and 10)
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 10)
Cin Maximum Input Capacitance
Guaranteed Limit
VCC – 55 to
V
25_C
v 85_C v 125_C
2.0 10
9
8
3.0 15 14 12
4.5 30 28 25
6.0 50 45 40
2.0 175 225 275
3.0 100 110 125
4.5 40 50 60
6.0 30 40 50
2.0 160 200 240
3.0 90
130 160
4.5 30 40 48
6.0 25 30 40
2.0 160 200 240
3.0 90
130 160
4.5 30 40 48
6.0 25 30 40
2.0 160 200 240
3.0 90
130 160
4.5 30 40 48
6.0 25 30 40
2.0 75
3.0 27
4.5 15
6.0 13
95 110
32 36
19 22
16 19
— 10 10 10
CPD Power Dissipation Capacitance (Per Package)*
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
Typical @ 25°C, VCC = 5.0 V
40
PIN DESCRIPTIONS
Unit
MHz
ns
ns
ns
ns
ns
pF
pF
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Active−low shift register reset. A low level
applied to this input resets the shift register to a low level,
but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low−to−high transition on this
input shifts data on the Serial Data Input into the shift
register and data in stage H is shifted out QH, being
replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low−to−high transition on this input loads
the parallel data on inputs A−H into the input latch.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last
stage of the shift register.
http://onsemi.com
5
5 Page 
MC74HC597A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
0.15 (0.006) T U S
2X L/2 16
L
PIN 1
IDENT.
1
0.15 (0.006) T U S
0.10 (0.004)
−T− SEATING
PLANE
D
C
16X K REF
0.10 (0.004) M T U S V S
9
B
−U− J
8
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
K
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
J1 ÇÇÇÇÉÉK1ÇÇÉÉ
SECTION N−N
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.25 (0.010)
DETERMINED AT DATUM PLANE −W−.
A
−V−
G
M
N
F
DETAIL E
H DETAIL E
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT
7.06
1
16X
0.36
16X
1.26
0.65
PITCH
DIMENSIONS: MILLIMETERS
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11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MC74HC597A.PDF ] | |
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