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PDF SN74LS163A Data sheet ( Hoja de datos )
| Número de pieza | SN74LS163A | |
| Descripción | BCD Decade Counters / 4-Bit Binary Counters | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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SN74LS161A, SN74LS163A
BCD Decade Counters/
4−Bit Binary Counters
The LS161A/163A are high-speed 4-bit synchronous counters.
They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency
division and other applications. The LS161A and LS163A count
modulo 16 (binary).
The LS161A has an asynchronous Master Reset (Clear) input that
overrides, and is independent of, the clock and all other control inputs.
The LS163A has a Synchronous Reset (Clear) input that overrides all
other control inputs, but is active only during the rising clock edge.
Asynchronous Reset
Synchronous Reset
Binary (Modulo 16)
LS161A
LS163A
• Synchronous Counting and Loading
• Two Count Enable Inputs for High Speed Synchronous Expansion
• Terminal Count Fully Decoded
• Edge-Triggered Operation
• Typical Count Rate of 35 MHz
• ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min Typ Max Unit
VCC Supply Voltage
TA Operating Ambient
Temperature Range
4.75 5.0 5.25
V
0 25 70 °C
IOH Output Current − High
IOL Output Current − Low
− 0.4
8.0
mA
mA
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 2
1
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
Package
Shipping
SN74LS161AN
16 Pin DIP 2000 Units/Box
SN74LS161AD
SOIC−16
38 Units/Rail
SN74LS161ADR2 SOIC−16 2500/Tape & Reel
SN74LS161AM
SOEIAJ−16
See Note 1
SN74LS161AMEL SOEIAJ−16
See Note 1
SN74LS163AN
16 Pin DIP 2000 Units/Box
SN74LS163AD
SOIC−16
38 Units/Rail
SN74LS163ADR2 SOIC−16 2500/Tape & Reel
SN74LS163AM
SOEIAJ−16
See Note 1
SN74LS163AMEL SOEIAJ−16
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
Publication Order Number:
SN74LS161A/D
1 page  
SN74LS161A, SN74LS163A
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay
Clock to TC
Propagation Delay
Clock to Q
Propagation Delay
CET to TC
MR or SR to Q
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
Parameter
tWCP
Clock Pulse Width Low
tW MR or SR Pulse Width
ts Setup Time, other*
ts Setup Time PE or SR
th Hold Time, data
th Hold Time, other
trec Recovery Time MR to CP
*CEP, CET, or DATA
Limits
Min Typ Max
25 32
20 35
18 35
13 24
18 27
9.0 14
9.0 14
20 28
Unit
MHz
ns
ns
ns
ns
Limits
Min Typ Max
25
20
20
25
3
0
15
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
tW(H)
tW(L)
CP 1.3 V
tPHL
1.3 V
tPLH
Other conditions:
PE = MR (SR) = H
CEP = CET = H
Q 1.3 V
1.3 V
Figure 1. Clock to Output Delays, Count
Frequency, and Clock Pulse Width
MR 1.3 V
CP
Q0 V Q1 V Q2 V Q3
tW
tPHL
trec
1.3 V
Other conditions:
PE = L
P0 = P1 = P2 = P3 = H
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
http://onsemi.com
5
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| PDF Descargar | [ Datasheet SN74LS163A.PDF ] | |
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