PDF MC74HC20A Data sheet ( Hoja de datos )

Número de pieza	MC74HC20A
Descripción	Dual 4-Input NAND Gate
Fabricantes	ON Semiconductor
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No Preview Available ! MC74HC20A Dual 4-Input NAND Gate High−Performance Silicon−Gate CMOS The MC74HC20A is identical in pinout to the LS20. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 V to 6 V • Low Input Current: 1 mA • High Noise Immunity Characteristic of CMOS Devices • These are Pb−Free Devices • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable A1 B1 C1 D1 1 2 4 5 A2 B2 C2 D2 9 10 12 13 6 Y1 Y = ABCD 8 Y1 PIN 14 = VCC PIN 7 = GND PINS 3, 11 = NO CONNECTION Figure 1. Logic Diagram http://onsemi.com 14 1 14 SOIC−14 D SUFFIX CASE 751A 1 MARKING DIAGRAMS HC20AG AWLYWW 14 1 TSSOP−14 DT SUFFIX CASE 948G 14 HC 20A ALYWG G 1 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT A1 B1 NC C1 D1 Y1 GND 1 2 3 4 5 6 7 14 VCC 13 D2 12 C2 11 NC 10 B2 9 A2 8 Y2 FUNCTION TABLE Inputs Output A BC D Y L XXX X LXX XXL X XXX L H HH H H H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2013 June, 2013 − Rev. 2 1 Publication Order Number: MC74HC20A/D 1 page MC74HC20A PACKAGE DIMENSIONS 0.15 (0.006) T U S 2X L/2 14 L PIN 1 IDENT. 1 TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) M T U S V S N 8 B −U− N 0.25 (0.010) M F 7 DETAIL E 0.15 (0.006) T U S A −V− K J J1 ÇÇÉÉÇÇÉÉK1ÇÇÉÉ SECTION N−N 0.10 (0.004) −T− SEATING PLANE D C G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 −W− J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 5 Page

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