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PDF NSBC113EDXV6 Data sheet ( Hoja de datos )
| Número de pieza | NSBC113EDXV6 | |
| Descripción | Dual NPN Bias Resistor Transistors | |
| Fabricantes | ON Semiconductor | |
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MUN5230DW1,
NSBC113EDXV6
Dual NPN Bias Resistor
Transistors
R1 = 1 kW, R2 = 1 kW
NPN Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25C, common for Q1 and Q2, unless otherwise noted)
Rating
Symbol
Max
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current − Continuous IC 100 mAdc
Input Forward Voltage
VIN(fwd)
10
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device
Package
Shipping†
MUN5230DW1T1G,
SMUN5230DW1T1G
SOT−363
3,000/Tape & Reel
NSBC113EDXV6T1G
SOT−563
4,000/Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
http://onsemi.com
PIN CONNECTIONS
(3) (2) (1)
R1
Q1
R2 R1
(4) (5)
R2
Q2
(6)
MARKING DIAGRAMS
SOT−363
CASE 419B
6
7G M G
G
1
SOT−563
CASE 463A
7G M G
G
1
7G = Specific Device Code
M = Date Code*
G = Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 0
1
Publication Order Number:
DTC113ED/D
1 page  
MUN5230DW1, NSBC113EDXV6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE W
D
e
654
HE −E−
123
b 6 PL
0.2 (0.008) M E M
A3
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX
A 0.80 0.95 1.10 0.031 0.037 0.043
A1 0.00 0.05 0.10 0.000 0.002 0.004
A3 0.20 REF
0.008 REF
b 0.10 0.21 0.30 0.004 0.008 0.012
C 0.10 0.14 0.25 0.004 0.005 0.010
D 1.80 2.00 2.20 0.070 0.078 0.086
E 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC
0.026 BSC
L 0.10 0.20 0.30 0.004 0.008 0.012
HE 2.00 2.10 2.20 0.078 0.082 0.086
C
A1 L
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.40
0.0157
0.65
0.025
1.9
0.0748
ǒ ǓSCALE 20:1
mm
inches
SC−88/SC70−6/SOT−363
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet NSBC113EDXV6.PDF ] | |
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