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PDF NCP81071 Data sheet ( Hoja de datos )
| Número de pieza | NCP81071 | |
| Descripción | Dual 5A High Speed Low-Side MOSFET Drivers | |
| Fabricantes | ON Semiconductor | |
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NCP81071
Dual 5 A High Speed
Low-Side MOSFET Drivers
with Enable
NCP81071 is a high speed dual low−side MOSFETs driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver 5 A peak current at the Miller plateau region to help
reduce the Miller effect during MOSFETs switching transition. This
driver also provides enable functions to give users better control
capability in different applications. ENA and ENB are implemented
on pin 1 and pin 8 which were previously unused in the industry
standard pin−out. They are internally pulled up to driver’s input
voltage for active high logic and can be left open for standard
operations. This part is available in MSOP8−EP package, SOIC8
package and WDFN8 3 mm x 3 mm package.
Features
• High Current Drive Capability ±5 A
• TTL/CMOS Compatible Inputs Independent of Supply Voltage
• Industry Standard Pin−out
• High Reverse Current Capability (6 A) Peak
• Enable Functions for Each Driver
• 8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load
• Typical Propagation Delay Times of 20 ns with Input Falling and
20 ns with Input Rising
• Input Voltage from 4.5 V to 20 V
• Dual Outputs can be Paralleled for Higher Drive Current
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• Server Power
• Telecommunication, Datacenter Power
• Synchronous Rectifier
• Switch Mode Power Supply
• DC/DC Converter
• Power Factor Correction
• Motor Drive
• Renewable Energy, Solar Inverter
www.onsemi.com
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
XXXX
ALYW
G
1
MSOP−8
Z SUFFIX
CASE 846AM
XXXX
AYW
G
1
WDFN8
MN SUFFIX
CASE 511CD
1
XX MG
G
XX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
ENA
8
ENB
INA OUTA
GND
VDD
INB OUTB
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 3
1
Publication Order Number:
NCP81071/D
1 page  
NCP81071
Table 6. ELECTRICAL CHARACTERISTICS
(Typical values: VDD =12 V, 1 mF from VDD to GND, TA = TJ = −40°C to 140°C, typical at TAMB = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Units
SUPPLY VOLTAGE
VDD Under Voltage Lockout (rising)
VDD Under Voltage Lockout
(hysteresis)
VCCR
VCCH
VDD rising
3.5 4.0 4.5
400
V
mV
Operating Current (no switching)
IDD INA = 0, INB = 5 V, ENA = ENB = 0
INA = 5 V, INB = 0, ENA = ENB = 0
INA = 0, INB = 5 V, ENA = ENB = 5 V
INA = 5 V, INB = 0, ENA = ENB = 5 V
1.4 3
mA
VDD Under Voltage Lockout to Output
Delay (Note 2)
VDD rising
10 ms
INPUTS
High Threshold
Low Threshold
INA, INB Pull−Up Resistance
VthH
VthL
Input rising from logic low
1.8 2.0 2.2
Input falling from logic high
0.8 1.0 1.2
OUTA = OUTB = Inverter Configuration
200
V
V
kW
INA, INB Pull−Down Resistance
OUTA = OUTB = Buffer Configuration
200
kW
OUTPUTS
Output Resistance High
Output Resistance Low
Peak Source Current (Note 3)
ROH
ROL
ISource
IOUT = −10 mA
IOUT = +10 mA
OUTA/OUTB = GND
200 ns Pulse
0.8 2
0.8 2
5
W
W
A
Miller Plateau Source Current (Note 3)
ISource
OUTA/OUTB = 5.0 V
200 ns Pulse
4.5 A
Peak Sink Current (Note 3)
ISink OUTA/OUTB = VDD
200 ns Pulse
5A
Miller Plateau Sink Current (Note 3)
ISink OUTA/OUTB = 5.0 V
200 ns Pulse
3.5 A
ENABLE
High−Level Input Voltage
Low−Level Input Voltage
ENA, ENB pull−up resistance
VIN_H
VIN_L
Low to High Transition
High to Low Transition
1.8 2.0 2.2
0.8 1.0 1.2
200
V
V
kW
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
td3 CLoad = 1.8 nF
16 20 29
ns
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
td4 CLoad = 1.8 nF
16 20 29
ns
SWITCHING CHARACTERISTICS
Propagation Delay Time Low to High,
IN Rising (IN to OUT) (Notes 2, 4)
td1 CLoad = 1.8 nF
16 20 29
ns
Propagation Delay Time High to Low,
IN Falling (IN to OUT) (Notes 2, 4)
td2 CLoad = 1.8 nF
16 20 29
ns
Rise Time (Note 4)
Fall Time (Note 4)
Delay Matching between 2 Channels
(Note 5)
tr CLoad = 1.8 nF
tf CLoad = 1.8 nF
tm INA = INB, OUTA and OUTB at 50%
Transition Point
8 15
8 15
14
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Not production tested, guaranteed by design and statistical analysis.
4. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.
5. Guaranteed by characterization.
www.onsemi.com
5
5 Page 
NCP81071
LAYOUT GUIDELINES
The switching performance of NCP81071 highly depends
on the design of PCB board. The following layout design
guidelines are recommended when designing boards using
these high speed drivers.
Place the driver as close as possible to the driven
MOSFET.
Place the bypass capacitor between VDD and GND as
close as possible to the driver to improve the noise filtering.
It is preferred to use low inductance components such as
chip capacitor and chip resistor. If vias are used, connect
several paralleled vias to reduce the inductance of the vias.
Minimize the turn-on/sourcing current and
turn-off/sinking current paths in order to minimize stray
inductance. Otherwise high di/dt established in these loops
with stray inductance can induce significant voltage spikes
on the output of the driver and MOSFET Gate terminal.
Keep power loops as short as possible by paralleling the
source and return traces (flux cancellation).
Keep low level signal lines away from high level power
lines with a lot of switching noise.
Place a ground plane for better noise shielding. Beside
noise shielding, ground plane is also useful for heat
dissipation.
NCP81071 DFN and MSOP package have thermal pad
for: 1) quiet GND for all the driver circuits; 2) heat sink for
the driver. This pad must be connected to a ground plane and
no switching currents from the driven MOSFET should pass
through the ground plane under the driver. To maximize the
heatsinking capability, it is recommended several ground
layers are added to connect to the ground plane and thermal
pad. A via array within the area of package can conduct the
heat from the package to the ground layers and the whole
PCB board. The number of vias and the size of ground plane
are determined by the power dissipation of NCP81071
(VDD voltage, switching frequency and load condition), the
air flow condition and its maximum junction temperature.
ORDERING INFORMATION
Part Number
Output Configuration
Temperature Range (5C)
Package Type
Shipping†
NCP81071ADR2G
dual inverting
NCP81071BDR2G
NCP81071CDR2G
dual non inverting
One inverting
one non inverting
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP81071AZR2G
dual inverting
NCP81071BZR2G
NCP81071CZR2G
dual non inverting
One inverting
one non inverting
−40 to +140
MSOP8 EP
(Pb−Free)
3000 / Tape & Reel
NCP81071AMNTXG
dual inverting
NCP81071BMNTXG
NCP81071CMNTXG
dual non inverting
One inverting
one non inverting
WDFN8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NCP81071.PDF ] | |
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