|
|
PDF CS5307 Data sheet ( Hoja de datos )
| Número de pieza | CS5307 | |
| Descripción | Four-Phase VRM 9.0 Buck Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CS5307 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
CS5307
Four−Phase VRM 9.0
Buck Controller
Multiphase controllers provide fast, accurate regulation with the
control features required to power the next generation of processors in
desktop, workstation and server applications. Combined with external
gate drivers and power components, the CS5307 implements a
compact, highly integrated buck converter. Enhanced V2™ control
inherently compensates for variations in both line and load. Current
sharing between phases is achieved by Peak Current Sharing.
The CS5307 includes Power Good with a programmable lower
threshold.
Applications include Embedded Processor Power and low
voltage/high current power supplies.
Features
• Switching Regulator Controller
− Lossless Current Sensing
− Enhanced V2 Control Method Provides Excellent Regulation
and Fast Transient Response
− Programmable 200 to 800 kHz Switching Frequency (Per Phase)
− Duty Cycle − 0% to 100%
− Programmable Adaptive Voltage Positioning Reduces Output
Capacitor Requirements
− Programmable Soft Start
• Accurate Current Sharing
• Protection Features
− Pulse−by−Pulse Current Limit for Each Phase
− Programmable Hiccup Overcurrent Protection
− All “1” DAC Code Fault
− Processor Overvoltage Protection through Bottom MOSFETs
− Undervoltage Lockout
• System Power Management
− 5−Bit DAC With 1.0% Tolerance Compatible with VRM 9.0
− Power Good Output
− Programmable Power Good Lower Threshold
− Guaranteed Startup at −20°C
http://onsemi.com
24
1
SO−24L
DW SUFFIX
CASE 751E
MARKING DIAGRAM
24
CS5307
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
GND
OCSET
ROSC
CS1
CS2
CS3
CS4
CSREF
VDRP
VFB
COMP
SS
24
VCC
GATE1
GATE2
GATE3
GATE4
VID0
VID1
VID2
VID3
VID4
PWRGDS
PWRGD
ORDERING INFORMATION
Device
Package
Shipping
CS5307GDW24 SO−24L
30 Units/Rail
CS5307GDWR24 SO−24L 1000 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 9
1
Publication Order Number:
CS5307/D
1 page  
CS5307
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEx = 100 pF,
CCOMP = 0.01μF, CSS = 0.1μF, CVCC = 0.1μF, RROSC = 32.4 kΩ, VOCSET = 0.54 V, DAC Code 01110; unless otherwise stated.)
Parameter
Test Conditions
Min Typ Max Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open or Pull−Up to Internal 3.3 V or External Voltage 12 V) (continued)
Pull−Up Voltage
1.0 MΩ to GND
2.5 2.7 3.0 V
Power Good Output
Upper Threshold
Force PWRGDS
1.876 (−5%)
1.975
2.074 (+5%)
V
Lower Threshold
Switch Leakage Current
Delay
Force PWRGDS
VCC = 14 V, PWRGDS = 1.4 V
PWRGDS low to PWRGD low
−5%
−
100
VID/2
0.1
800
+5%
1.0
2000
V
μA
μs
Output Low Voltage
PWRGDS = 1.0 V,
IPWRGD = 4.0 mA
Voltage Feedback Error Amplifier
− 0.15 0.4 V
VFB Bias Current
Comp Source Current
Comp Sink Current
Transconductance
Output Impedance
Note 2
COMP = 0.5 V to 2.0 V,
VFB = 1.8 V, DAC = 00000
COMP = 0.5 V to 2.0 V,
VFB = 1.15 V, DAC = 11110
−10 μA < ICOMP < +10 μA, Note 3
−
9.9
15
15
200
−
10.25
30
30
500
2.5
10.6 μA
60 μA
60 μA
750 μmho
− MΩ
Open Loop DC Gain
Note 3
45 95
− dB
Unity Gain Bandwidth
− − 50 − kHZ
PSRR @ 1.0 kHz
− − 60 − dB
COMP Max Voltage
COMP Min Voltage
PWM Comparators
VFB = 0 V
VFB = 1.6 V
2.4 2.7
−V
− 50 150 mV
Minimum Pulse Width
Measured from CSx to GATEx,
VFB = CSREF = 0.5 V,
COMP = 0.5 V,
60 mV step on CSx;
measure at GATEx = 1.0 V
−
40 70 ns
Transient Response Time
Measured from CSREF to GATEx,
COMP = 2.1 V,
CSx = CSREF = 0.5 V,
CSREF stepped
from 1.2 V − 2.0 V
−
40 60 ns
Channel Start−Up Offset
CSx = CSREF = VFB = 0 V,
350 600 750 mV
measure VCOMP when GATEx
switch high
Artificial Ramp Amplitude
50% Duty Cycle, Note 3
− 115 − mV
Gates
High Voltage
Measure GATEx
IGATEx = 1.0 mA
2.0 2.6 3.0 V
Low Voltage
Measure GATEx, IGATEx = 1.0 mA
−
0.5 0.7 V
2. The VFB Bias Current changes with the value of ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
http://onsemi.com
5
5 Page 
CS5307
APPLICATIONS INFORMATION
Overview
The CS5307 DC/DC controller from ON Semiconductor
was developed using the Enhanced V2 topology. Enhanced
V2 combines the original V2 topology with peak
current−mode control for fast transient response and current
sensing capability. The addition of an internal PWM ramp
and implementation of fast−feedback directly from Vcore
has improved transient response and simplified design. The
CS5307 includes Power Good (PWRGD), providing a
highly integrated solution to simplify design, minimize
circuit board area, and reduce overall system cost.
Two advantages of a multi−phase converter over a
single−phase converter are current sharing and increased
apparent output frequency. Current sharing allows the designer
to use less inductance in each phase than would be required in
a single−phase converter. The smaller inductor will produce
larger ripple currents but the total per−phase power dissipation
is reduced because the RMS current is lower. Transient
response is improved because the control loop will measure
and adjust the current faster in a smaller output inductor.
Increased apparent output frequency is desirable because the
off− time and the ripple voltage of the multi−phase converter
will be less than that of a single−phase converter.
Fixed Frequency Multi−Phase Control
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5307 controller uses four−phase, fixed−frequency,
Enhanced V2 architecture to measure and control currents in
individual phases. Each phase is delayed 90° from the
previous phase. Normally, GATEx transitions to a high
voltage at the beginning of each oscillator cycle. Inductor
current ramps up until the combination of the current sense
signal, the internal ramp and the output voltage ripple trip
the PWM comparator and bring GATEx low. Once GATEx
goes low, it will remain low until the beginning of the next
oscillator cycle. While GATEx is high, the Enhanced V2
loop will respond to line and load variations. On the other
hand, once GATEx is low, the loop cannot respond until the
beginning of the next PWM cycle. Therefore, constant
frequency Enhanced V2 will typically respond to
disturbances within the off−time of the converter.
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional input (CSx) for
inductor current information has been added to the V2 loop
for each phase as shown in Figure 14. The triangular
inductor current is measured differentially across RS,
amplified by CSA and summed with the channel startup
offset, the internal ramp and the output voltage at the
non−inverting input of the PWM comparator. The purpose
of the internal ramp is to compensate for propagation delays
in the CS5307. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The CS5307 provides a CSx
input for each phase, but the CSREF and COMP inputs are
common to all phases. Current sharing is accomplished by
referencing all phases to the same CSREF and COMP pins,
so that a phase with a larger current signal will turn off earlier
than a phase with a smaller current signal.
SWNODE
Lx
VOUT
(VCORE)
+
RLx
RSx
+
x = 1, 2, 3, or 4
CSx + COx
CSA
−
CSREF
Internal Ramp
“Fast−Feedback”
Connection
VFB
DAC
Out
−
E.A.
+
Channel
Start−Up
Offset
COMP
+
−
PWM
COMP
To F/F
Reset
Figure 14. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp
http://onsemi.com
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CS5307.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CS5301 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5301GDW32 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5301GDWR32 | Three-Phase Buck Controller with Integrated Gate Drivers and Power Good | ON Semiconductor |
| CS5302 | Two-Phase Buck Controller | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |