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EM428M1644RTA fiches techniques PDF

Eorex - Double DATA RATE SDRAM

Numéro de référence EM428M1644RTA
Description Double DATA RATE SDRAM
Fabricant Eorex 
Logo Eorex 





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EM428M1644RTA fiche technique
eorex
EM428M1644RTA
128Mb (2M×4Bank×16)
Double DATA RATE SDRAM
Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• VDD/VDDQ= 2.5V ±0.2V for (-75 and -6)
• VDD/VDDQ= 2.6V ±0.1V for (-5 )
• 2.5V SSTL-2 compatible I/O
• Burst Length (B/L) of 2, 4, 8
• 2,2.5,3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• DLL aligns DQ & DQS transitions with CLK’s
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms
Ordering Information
Description
The EM428M1644RTA is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 134,217,728 bits which
organized as 2Meg words x 4 banks by 16 bits.
The 128Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
Part No
EM428M1644RTA-75F
EM428M1644RTA-6F
EM428M1644RTA-5F
Organization Max. Freq
8M X 16
133MHz @CL2.5
8M X 16
166MHz @CL2.5
8M X 16
200MHz @CL3
EM 42 8M 16 4 4 R T A - X F E
Package
66pin TSOP(ll)
66pin TSOP(ll)
66pin TSOP(ll)
Grade
Commercial
Commercial
Commercial
Pb
Free
Free
Free
EOREX Memory
DDR SDRAM
Density
BM: 32 Mega
AM: 16 Mega
8M: 8 Mega
4M: 4 Mega
2M: 2 Mega
1M: 1 Mega
Organization
16: x16
Refresh
4: 4K
Bank
4: 4Bank
Grade
E: extended temp.
Package
F: Pb-free
Min Cycle Time (Max Freq.)
-5: 5ns (200MHz)
-6: 6ns (166MHz)
-75: 7.5ns (133MHz)
Revision
A: 1st
Package
T: TSOP
Interface
R: 2.5V
Apr. 2007
1/20
www.eorex.com

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