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PDF ESD8118 Data sheet ( Hoja de datos )
| Número de pieza | ESD8118 | |
| Descripción | ESD Protection Diode | |
| Fabricantes | ON Semiconductor | |
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ESD8118
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8118 transient voltage suppressor is specifically designed
to protect four high speed data pairs from ESD. Ultra−low capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
• Low Capacitance (0.35 pF Max, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• HDMI 1.3/1.4/2.0
• Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
www.onsemi.com
MARKING
DIAGRAM
UDFN10
CASE 517CY
ACMG
G
PIN CONFIGURATION
I/O I/O I/O
10 9 8
I/O
7
123
I/O GND I/O
45
I/O GND
6
I/O
ORDERING INFORMATION
Device
Package
Shipping
ESD8118MUTAG UDFN10 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0
1
Publication Order Number:
ESD8118/D
1 page  
ESD8118
20 10 −20
18 −18
10
16 8
14
12 6
10
84
6
42
2
00
0 2 4 6 8 10 12 14 16 18 20
VC, VOLTAGE (V)
Figure 6. Positive TLP I−V Curve
−16
−14
−12
−10
−8
−6
−4
−2
0
0
8
6
4
2
2 4 6 8 10 12 14 16 18
VC, VOLTAGE (V)
Figure 7. Negative TLP I−V Curve
0
20
NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 8. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 9 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
L
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM VM
VC DUT
Oscilloscope
Figure 8. Simplified Schematic of a Typical TLP
System
Figure 9. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
www.onsemi.com
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ESD8118.PDF ] | |
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