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PDF MMDF4207 Data sheet ( Hoja de datos )
| Número de pieza | MMDF4207 | |
| Descripción | Dual P-Channel Field Effect Transistors | |
| Fabricantes | ON Semiconductor | |
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MMDF4207
Dual P-Channel
Field Effect Transistors
Medium Power Surface Mount Products
These devices are an advanced series of power MOSFETs which
utilize ON Semiconductor’s latest MOSFET technology process to
achieve the lowest possible on−resistance per silicon area. They are
capable of withstanding high energy in the avalanche and
commutation modes and the drain−to−source diode has a very low
reverse recovery time. These devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are dc−dc converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
• Ultra Low RDS(on) Provides Higher Efficiency and
Extends Battery Life in Portable Applications
• Characterized Over a Wide Range of Power Ratings
• Logic Level Gate Drive − Can Be Driven by
Logic ICs
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, with Soft Recovery
• IDSS Specified at Elevated Temperature
• Miniature SO−8 Surface Mount Package −
Saves Board Space
http://onsemi.com
DUAL POWER MOSFET
6.2 AMPERES
20 VOLTS
RDS(on) = 0.033 Ω
D
G
S
8
1
SO−8
CASE 751
STYLE 11
SOURCE 1
GATE 1
SOURCE 2
GATE 2
18
27
36
45
TOP VIEW
DRAIN 1
DRAIN 1
DRAIN 2
DRAIN 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 3
1
Publication Order Number:
MMDF4207/D
1 page  
MMDF4207
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
6000
5000 Ciss
VDS = 0 V VGS = 0 V
TJ = 25°C
4000 Crss
3000
2000
1000
0
10
Crss
50
5
VGS VDS
Ciss
Coss
10 15
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
20
http://onsemi.com
5
5 Page 
MMDF4207
PACKAGE DIMENSIONS
−X−
A
SOIC−8 NB
CASE 751−07
ISSUE AK
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
J
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT*
1.52
0.060
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
DIM MIN MAX
A 4.80 5.00
B 3.80 4.00
C 1.35 1.75
D 0.33 0.51
G 1.27 BSC
H 0.10 0.25
J 0.19 0.25
K 0.40 1.27
M 0_ 8_
N 0.25 0.50
S 5.80 6.20
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
INCHES
MIN MAX
0.189 0.197
0.150 0.157
0.053 0.069
0.013 0.020
0.050 BSC
0.004 0.010
0.007 0.010
0.016 0.050
0_ 8_
0.010 0.020
0.228 0.244
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
HDTMOS is a trademark of Semiconductor Components Industries, LLC.
Thermal Clad is a trademark of the Bergquist Company.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MMDF4207/D
11 Page | ||
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