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PDF NCV7519 Data sheet ( Hoja de datos )
| Número de pieza | NCV7519 | |
| Descripción | Hex Low-side MOSFET Pre-driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV7519, NCV7519A
FLEXMOS] Hex Low-side
MOSFET Pre-driver
The NCV7519/A programmable six channel low−side MOSFET
pre−driver is one of a family of FLEXMOS automotive grade products
for driving logic−level MOSFETs. The product is controllable by a
combination of serial SPI and parallel inputs. The device offers 3.3 V/
5 V compatible inputs and the serial output driver can be powered
from either 3.3 V or 5 V. An internal power−on reset provides
controlled power up. A reset input allows external re−initialization and
an enable input allows all outputs and diagnostics to be simultaneously
disabled.
Each channel independently monitors its external MOSFET’s drain
voltage for fault conditions. Shorted load fault detection thresholds are
fully programmable using an externally programmed reference
voltage and a combination of discrete internal ratio values. The ratio
values are SPI selectable and allow different detection thresholds for
each channel.
Fault recovery operation for each channel is programmable and may
be selected for latch−off or automatic retry. Status information for
each channel is 3−bit encoded by fault type and is available through
SPI communication.
The FLEXMOS family of products offers application scalability
through choice of external MOSFETs.
Features
• 16−bit SPI with Parity and Frame Error Detection
• 3.3 V/5 V Compatible Parallel and Serial Control Inputs
• 3.3 V/5 V Compatible Serial Output Driver
• Reset and Enable Inputs
• Open−drain Fault Flag
• Priority Encoded Diagnostics with Latched Unique Fault Type Data
♦ Shorted Load, Short to GND
♦ Open Load
♦ On and Off State Pulsed Mode Diagnostics
• Ratiometric Diagnostic References and Currents
• Programmable
♦ Shorted Load Fault Detection Thresholds
♦ Fault Recovery Mode
♦ Blanking Timers
• Wettable Flanks Pb−Free Packaging
• Commercial Vehicle Capable
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This is a Pb−Free Device
Benefits
• Scalable to Load by Choice of External MOSFET
www.onsemi.com
QFN32
MW SUFFIX
CASE 488AM
QFN32
MW SUFFIX
CASE 485CZ
MARKING DIAGRAM
1
NCV7519x
AWLYYWWG
G
x = blank or A
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 36 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 2
1
Publication Order Number:
NCV7519/D
1 page  
NCV7519, NCV7519A
MAXIMUM RATINGS (Voltages are with respect to device substrate.)
Rating
Value
Unit
DC Supply − VLOAD
−0.3 to 45
V
DC Supply − VCC1, VCC2, VDD
Difference Between VCC1 and VCC2
Difference Between GND (Substrate) and VSS
Drain Input Clamp Forward Voltage Transient (≤2 ms, ≤1% duty)
−0.3 to 5.8
±0.3
±0.3
78
V
V
V
V
Drain Input Clamp Forward Current Transient (≤2 ms, ≤1% duty)
10 mA
Drain Input Clamp Energy Repetitive (≤2 ms, ≤1% duty)
1.56 mJ
Drain Input Clamp Reverse Current VDRNX ≥ −1.0 V
Input Voltage (Any Input Other Than Drain)
−50
−0.3 to 5.8
mA
V
Output Voltage (Any Output)
−0.3 to 5.8
V
Junction Temperature, TJ
Storage Temperature, TSTG
Peak Reflow Soldering Temperature: Lead−free 60 to 150 seconds at 217°C (Note 1)
−40 to 150
−65 to 150
260 peak
°C
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ATTRIBUTES
Characteristic
Value
ESD Capability
Human Body Model per AEC−Q100−002
Machine Model per AEC−Q100−003
Drain Feedback Pins (Note 3)
All Other Pins
≥ ±4.0 kV
≥ ±2.0 kV
≥ ±200 V
Moisture Sensitivity
(Note 2)
MSL3
Package Thermal Resistance − Still−air
Junction−to−Ambient, RqJA
Junction−to−Exposed Pad, RYJPAD
(Note 4)
(Note 5)
95°C/W
46°C/W
3.2°C/W
2. See or download ON Semiconductor’s Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
3. With GND & VSS pins tied together − path between drain feedback pins and GND, or between drain feedback pins.
4. Based on JESD51−3, 1.2 mm thick FR4, 2S0P PCB, 2 oz. signal, 20 thermal vias to 400 mm2 spreader on bottom layer.
5. Based on JESD51−7, 1.2 mm thick FR4, 1S2P PCB, 2 oz. signal, 20 thermal vias to 80 x 80 mm 1 oz. internal spreader planes.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
MIN
MAX
Unit
VLOAD
Diagnostic References and Currents Power Supply Voltage
7.5 36.0 V
VDRNX
Drain Input Feedback Voltage
−0.3 60 V
VCC1
Main Power Supply Voltage
4.75 5.25 V
VCC2
Gate Drivers Power Supply Voltage
VCC1 − 0.3 VCC1 + 0.3
V
VDD Serial Output Driver Power Supply Voltage
3.0
VCC1
V
VFLTREF Fault Detect Threshold Reference Voltage
0.35 2.75 V
VIN High Logic High Input Voltage
2.0
VCC1
V
VIN Low Logic Low Input Voltage
0 0.8 V
TA Ambient Still−air Operating Temperature
−40 125 °C
tRESET
Startup Delay at Power−on Reset (POR) (Note 6)
500 − ms
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Minimum wait time until device is ready to accept serial input data.
www.onsemi.com
5
5 Page 
NCV7519, NCV7519A
When CSB goes low, frame error detection is initialized,
output data is transferred to the SPI, and the FLTB flag is
disabled and reset if previously set.
If a valid frame has been received when CSB goes high,
the last multiple of 16 bits received is decoded into
command data, and FLTB is re−enabled. The FLTB flag will
be set if a fault is detected.
If a frame or parity error is detected when CSB goes high,
new command data is ignored, and previous fault data
remains latched and available for retrieval during the next
valid frame. The FLTB flag will be set if a fault (not a frame
or parity error) is detected.
The interaction between CSB and FLTB facilitates fault
polling. When multiple NCV7519 devices are configured
for parallel SPI access with individual CSB addressing, the
device reporting a fault can be identified by pulsing each
CSB in turn.
CSB
SCLK
MSB
1
2
3
4 − 13
LSB
14 15 16
SI X B15
B14
B13
B12 − B3
B2 B1 B0
X
SO
B15 B14
B13
B12 − B3
B2 B1 B0 UKN Z
Note: X=Don’t Care, Z=Tri−State, UKN=Unknown Data
Figure 10. SPI Communication Frame Format
Serial Data and Register Structure
The 16−bit data received by the NCV7519 is decoded into
a 3−bit address, a 12−bit data word, and an odd parity bit
(Figure 11). The upper three bits, beginning with the
received MSB, are fully decoded to address one of eight
registers. The valid register addresses are shown in Table 1.
The input command structure is shown in Table 3. Each
register is later described in detail.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
MSB
LSB
ADDRESS
INPUT DATA + PARITY
ADDRESS ECHO
OUTPUT DATA + PARITY
MSB
LSB
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
Figure 11. SPI Data Format
www.onsemi.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCV7519.PDF ] | |
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