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PDF NCP5162 Data sheet ( Hoja de datos )

Número de pieza NCP5162
Descripción General Purpose Synchronous Buck Controller
Fabricantes ON Semiconductor 
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No Preview Available ! NCP5162 Hoja de datos, Descripción, Manual

NCP5162
General Purpose
Synchronous Buck Controller
The NCP5162 is a synchronous dual NChannel buck controller
designed to provide unprecedented transient response for today’s
demanding highdensity, highspeed logic. It operates using a
proprietary control method which allows a 100 ns response time to
load transients. The NCP5162 is designed to operate over a 916 V
range (VCC) using 12 V to power the IC and 5.0 V as the main supply
for conversion.
The NCP5162 is specifically designed for high performance core
logic. It includes the following features: 0.8% output tolerance, VCC
monitor, and programmable Soft Start capability. The NCP5162 is
available in a 16 pin surface mount package.
Features
Dual NChannel Design
Excess of 1.0 MHz Operation
100 ns Transient Response
2.0 A Gate Drivers
1.02 V Reference Voltage with 0.8% Tolerance
5.0 V & 12 V Operation
Remote Sense
Programmable Soft Start
Lossless Short Circuit Protection
VCC Monitor
V2Control Topology
Overvoltage Protection
http://onsemi.com
SO16
D SUFFIX
CASE 751B
MARKING
DIAGRAM
16
NCP5162
AWLYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
Disable
NC
NC
NC
SS
NC
COFF
VFFB
16
VFB
COMP
LGND
VCC1
VGATE(L)
PGND
VGATE(H)
VCC2
ORDERING INFORMATION
Device
NCP5162D
NCP5162DR2
Package
Shipping
SO16
SO16
48 Units/Rail
2500 Tape & Reel
© Semiconductor Components Industries, LLC, 2006
July, 2006 Rev. 4
1
Publication Order Number:
NCP5162/D

1 page




NCP5162 pdf
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO16
1
2, 3, 4, 6
5
7
8
9
10
11
12
13
14
15
16
PIN SYMBOL
Disable
NC
SS
COFF
VFFB
VCC2
VGATE(H)
PGND
VGATE(L)
VCC1
LGND
COMP
VFB
NCP5162
FUNCTION
This pin is internally pulled down to ground through a resistor,
providing a logic 0 if left open. When pulled to VCC, The output gate
drivers are pulled low, powering off the external output stage. At the
same time the Soft Start capacitor is slowly discharged by an internal
2.0 μA current source, setting the time out before the IC is restarted.
No connection.
Soft Start Pin. A capacitor from this pin to LGND in conjunction with
internal 60 μA current source provides Soft Start function for the
controller. This pin disables fault detect function during Soft Start.
When a fault is detected, the Soft Start capacitor is slowly discharged
by internal 2.0 μA current source setting the time out before trying to
restart the IC. Charge/discharge current ratio of 30 sets the duty cycle
for the IC when the regulator output is shorted.
A capacitor from this pin to ground sets the time duration for the on
board one shot, which is used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is
connected to the regulator output. The inner feedback loop
terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 3.0 A peak switching current. Internal
circuit prevents VGATE(H) and VGATE(L) from being in high state
simultaneously.
High current ground for the IC. The MOSFET drivers are referenced
to this pin. Input capacitor ground and the source of lower FET should
be tied to this pin.
Low FET driver pin capable of 3.0 A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be
provided externally to compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be connected
directly to the output or a remote sense trace.
http://onsemi.com
5

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NCP5162 arduino
NCP5162
M 5.00 ms
Trace 45.0 V from PC Power Supply (5.0 V/div.)
Trace 1Regulator Output Voltage (1.0 V/div.)
Figure 15. NCP5162 OVP Response to an
InputtoOutput Short Circuit by Pulling the Input
Voltage to Ground
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
16). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
VPower
Good
+
(R1
)
R2)
R2
0.65 V
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages less
than VPower Good.
5.0 V
VOUT
NCP5162
R1
10 k
R3
10 k
PN3904
R2
6.2 k
Power Good
PN3904
M 2.50 ms
Trace 3 12 V Input (VCC1) and (VCC2) (10 V/div.)
Trace 45.0 V Input (2.0 V/div.)
Trace 1Regulator Output Voltage (1.0 V/div.)
Trace 2Power Good Signal (2.0 V/div.)
Figure 17. NCP5162 During Power Up. Power
Good Signal is Activated when Output
Voltage Reaches 1.70 V
Slope Compensation
The V2 control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V2 control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch ontime.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
Figure 16. Implementing Power Good
with the NCP5162
http://onsemi.com
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