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PDF ISLA112P25M Data sheet ( Hoja de datos )
| Número de pieza | ISLA112P25M | |
| Descripción | Low Power 12-Bit ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Low Power 12-Bit, 250MSPS ADC
ISLA112P25M
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process.
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of various
parameters such as gain and offset.
Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA112P25MREP is available in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the full
military temperature range (-55°C to +125°C).
Applications
• Power Amplifier Linearization
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
Key Specifications
• SNR = 62.7dBFS for fIN = 105MHz (-1dBFS)
• SFDR = 67dBc for fIN = 105MHz (-1dBFS)
• Total Power Consumption
- 310mW @ 250MSPS (SDR Mode)
- 234mW @ 250MSPS (DDR Mode)
Features
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
VID Features
• Specifications per DSCC VID V62/10609
• Full Military Temperature Electrical Performance from
-55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
• Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
Block Diagram
CLKP
CLKN
VINP
VINN
VCM
CLOCK
GENERATION
CLKOUTP
CLKOUTN
SHA
1.25V
+
–
12-BIT
250 MSPS
ADC
SPI
CONTROL
DIGITAL
ERROR
CORRECTION
LVDS/CMOS
DRIVERS
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
November 17, 2011
FN7646.1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISLA112P25M
Table of Contents
Block Diagram ..................................................................................................................................... 1
Pin Configuration................................................................................................................................. 2
Pin Descriptions .................................................................................................................................. 2
Ordering Information .......................................................................................................................... 4
Absolute Maximum Ratings ................................................................................................................. 6
Thermal Information ........................................................................................................................... 6
Operating Conditions ........................................................................................................................... 6
Electrical Specifications ....................................................................................................................... 6
Digital Specifications ........................................................................................................................... 8
Timing Diagrams ................................................................................................................................. 9
Switching Specifications ...................................................................................................................... 9
Typical Performance Curves .............................................................................................................. 11
Theory of Operation........................................................................................................................... 14
Functional Description....................................................................................................................... 14
Power-On Calibration ........................................................................................................................ 14
User-Initiated Reset ......................................................................................................................... 15
Analog Input ................................................................................................................................... 15
Clock Input ..................................................................................................................................... 16
Jitter .............................................................................................................................................. 17
Voltage Reference ............................................................................................................................ 17
Digital Outputs ................................................................................................................................ 17
Over Range Indicator........................................................................................................................ 17
Power Dissipation............................................................................................................................. 17
Nap/Sleep ....................................................................................................................................... 17
Data Format .................................................................................................................................... 18
Serial Peripheral Interface ................................................................................................................ 20
SPI Physical Interface ....................................................................................................................... 20
SPI Configuration ............................................................................................................................. 21
Device Information........................................................................................................................... 21
Indexed Device Configuration/Control ................................................................................................. 21
Global Device Configuration/Control.................................................................................................... 22
SPI Memory Map.............................................................................................................................. 25
Equivalent Circuits............................................................................................................................. 26
ADC Evaluation Platform ................................................................................................................... 27
Layout Considerations ....................................................................................................................... 27
Split Ground and Power Planes........................................................................................................... 27
Clock Input Considerations ................................................................................................................ 27
Exposed Paddle................................................................................................................................ 27
Bypass and Filtering ......................................................................................................................... 27
LVDS Outputs .................................................................................................................................. 27
LVCMOS Outputs.............................................................................................................................. 28
Unused Inputs ................................................................................................................................. 28
Definitions ......................................................................................................................................... 28
Revision History ................................................................................................................................ 28
Products ............................................................................................................................................ 28
Package Outline Drawing .................................................................................................................. 29
5 FN7646.1
November 17, 2011
5 Page 
ISLA112P25M
Typical Performance Curves All Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade).
90
85
SFDR @ 125MSPS
80
75
SNR @ 125MSPS
70
65
60
SNR @ 250MSPS
55
SFDR @ 250MSPS
50
0
200M
400M
600M
800M
INPUT FREQUENCY (Hz)
1G
-50
-55
-60 HD2 @ 125MSPS
-65
HD2 @ 250MSPS
-70
-75
-80
-85
-90 HD3 @ 125MSPS
-95
-100
0
200M
HD3 @ 250MSPS
400M
600M
800M
INPUT FREQUENCY (Hz)
1G
FIGURE 3. SNR AND SFDR vs fIN
FIGURE 4. HD2 AND HD3 vs fIN
100
90
80
SFDRFS (dBFS)
70
60
50 SNRFS (dBFS)
40
30 SFDR (dBc)
20
10 SNR (dBc)
0
-60 -50 -40 -30 -20
INPUT AMPLITUDE (dBFS)
-10
FIGURE 5. SNR AND SFDR vs AIN
0
95
90
SFDR
85
80
75
70
SNR
65
60
40
70 100 130 160 190 220
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
250
-20
-30 HD2 (dBc)
-40
-50
-60
-70 HD3 (dBc)
-80 HD2 (dBFS)
-90
-100
-110 HD3 (dBFS)
-120
-60 -50 -40 -30 -20 -10
INPUT AMPLITUDE (dBFS)
FIGURE 6. HD2 AND HD3 vs AIN
0
-60
-70
HD3
-80
-90
-100
-110
HD2
-120
40
70 100 130 160 190 220
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs fSAMPLE
250
11 FN7646.1
November 17, 2011
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