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PDF ICS83940DI Data sheet ( Hoja de datos )
| Número de pieza | ICS83940DI | |
| Descripción | 1-to18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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Low Skew, 1-to18
LVPECL-to-LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 (83940DKILF)
ICS83940DI
DATA SHEET
General Description
The ICS83940DI is a low skew, 1-to-18 LVPECL- to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940DI has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines.
The ICS83940DI is characterized at full 3.3V and 2.5V or mixed 3.3V
core, 2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS83940DI ideal for
those clock distribution applications demanding well defined
performance and repeatability.
Block Diagram
CLK_SEL Pulldown
PCLK Pulldown
nPCLK Pullup/Pulldown
0
LVCMOS_CLK Pulldown
1
18
Q0:Q17
Features
• Eighteen LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• LVCMOS_CLK supports the following input types: LVCMOS or
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• For functional replacement part for 83940DKILF use 87016i
Pin Assignments
32 31 30 29 28 27 26 25
GND 1
24 Q6
GND 2
23 Q7
LVCMOS_CLK 3
22 Q8
CLK_SEL 4
PCLK 5
ICS83940DI
21 VDD
20 Q9
nPCLK 6
19 Q10
VDD 7
18 Q11
VDDO 8
17 GND
9 10 11 12 13 14 15 16
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1 24 Q6
2 23 Q7
3 22 Q8
4 ICS83940DI 21 VDD
5 20 Q9
6 19 Q10
7 18 Q11
8 17 GND
9 10 11 12 13 14 15 16
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS83940DYI REVISION C May 19, 2016
1
©2016 Integrated Device Technology, Inc.
1 page  
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4C. DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VIH Input High Voltage
LVCMOS_CLK
VIL Input Low Voltage
LVCMOS_CLK
IIN Input Current
VOH Output High Voltage
VOL Output Low Voltage
VPP
Peak-to-Peak Input Voltage;
NOTE 1
PCLK, nPCLK
IOH = -12mA
IOL = 12mA
VCMR
Common Mode Input
Voltage; NOTE 1, 2
PCLK, nPCLK
IDD Power Supply Current
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Minimum
2
1.8
300
Typical
Maximum
VDD
0.8
±200
0.5
Units
V
V
µA
V
V
1000
mV
VDD – 1.4
VDD – 0.6
25
V
mA
ICS83940DYI REVISION C May 19, 2016
5
©2016 Integrated Device Technology, Inc.
5 Page 
ICS83940DI Data Sheet
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS83940DYI REVISION C May 19, 2016
11
©2016 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS83940DI.PDF ] | |
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