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PDF ICS8530-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS8530-01 | |
| Descripción | Differential-to-3.3V LVPECL Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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Low Skew, 1-to16, Differential-to-3.3V
LVPECL Fanout Buffer
ICS8530-01
DATA SHEET
General Description
The ICS8530-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
ICS8530-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
• Sixteen differential 3.3V LVPECL outputs
• CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
• Output skew: 75ps (maximum)
• Part-to-part skew: 305ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK Pulldown
nCLK Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
ICS8530FY-01 REVISION G NOVEMBER 15, 2012
Pin Assignment
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
VCCO
ICS8530-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1 ©2012 Integrated Device Technology, Inc.
1 page  
ICS8530-01 Data Sheet
LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 106.25MHz
12kHz to 20MHz = 0.03ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
ICS8530FY-01 REVISION G NOVEMBER 15, 2012
5
©2012 Integrated Device Technology, Inc.
5 Page 
ICS8530-01 Data Sheet
LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8530-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 146mA = 505.89mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 16 * 30mW = 480mW
Total Power_MAX (3.465V, with all outputs switching) = 505.89mW + 480mW = 985.89mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 53.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.986W * 53.9°C/W = 123.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 48 Lead LQFP, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
53.9°C/W
1
47.7°C/W
2.5
45.0°C/W
ICS8530FY-01 REVISION G NOVEMBER 15, 2012
11
©2012 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS8530-01.PDF ] | |
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