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PDF ICS854S057BI Data sheet ( Hoja de datos )
| Número de pieza | ICS854S057BI | |
| Descripción | 4:1 or 2:1 LVDS Clock Multiplexer | |
| Fabricantes | Integrated Device Technology | |
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4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
ICS854S057BI
DATA SHEET
General Description
The ICS854S057BI is a 4:1 or 2:1 LVDS Clock
ICS Multiplexer which can operate up to 2GHz. The PCLK,
HiPerClockS™ nPCLK pairs can accept most standard differential
input levels. Internal termination is provided on each
differential input pair. The ICS854S057BI operates
using a 2.5V supply voltage. The fully differential architecture and
low propagation delay make it ideal for use in high speed
multiplexing applications. The select pins have internal pulldown
resistors. Leaving one input unconnected (pulled to logic low by the
internal resistor) will transform the device into a 2:1 multiplexer. The
SEL1 pin is the most significant bit and the binary number applied to
the select pins will select the same numbered data input (i.e., 00
selects PCLK0, nPCLK0).
Features
• High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
• One LVDS output pair
• Four selectable PCLK, nPCLK inputs with internal termination
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >2GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 800ps (maximum)
• Additive phase jitter, RMS: 0.065ps (typical)
• Full 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
50
VT2
50
PCLK2
nPCLK2
VT3
50
50 50
PCLK3
nPCLK3
SEL1 Pulldown
SEL0 Pulldown
00
01
10
11
Q
nQ
ICS854S057BGI REVISION A MARCH 29, 2010
Pin Assignment
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
ICS854S057BI
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
1 ©2010 Integrated Device Technology, Inc.
1 page  
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
ICS854S057BGI REVISION A MARCH 29, 2010
5
©2010 Integrated Device Technology, Inc.
5 Page 
ICS854S057BI Data Sheet
4:1, OR 2:1 LVDS CLOCK MULTIPLEXER W/INTERNAL INPUT TERMINATION
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S057BI.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S057BI is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 50mA = 131.25mW
• Power Dissipation for internal termination RT
Power (RT)MAX = 4 * (VPP_MAX)2 / RT_MIN = (1.2V)2 / 80Ω = 72mW
Total Power_MAX = 131.25mW + 72mW = 203.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.203W * 92.1°C/W = 103.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
92.1°C/W
1
86.5°C/W
2.5
83.0°C/W
ICS854S057BGI REVISION A MARCH 29, 2010
11
©2010 Integrated Device Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet ICS854S057BI.PDF ] | |
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