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PDF IDT82V3396 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V3396 | |
| Descripción | Dual Synchronous Ethernet Line Card PLL | |
| Fabricantes | Integrated Device Technology | |
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Dual Synchronous Ethernet Line Card
PLL
Short Form Datasheet
IDT82V3396
FEATURES
HIGHLIGHTS
• Dual PLL chip:
• Provides node clock for ITU-T G.8261/G.8262 Synchronous
Ethernet (SyncE)
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter
generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM
and 3G networks)
• Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applica-
tions
MAIN FEATURES
• Employs PLL architecture to feature excellent jitter performance
and minimize the number of external components
• Integrates 2 DPLLs; one can be used on the transmit path and the
other on the receive path
• Supports programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and
560 Hz
• Provides OUT1~OUT6 output clock frequencies up to 644.53125
MHz
• Includes 25MHz, 125 MHz and 156.25 MHz for CMOS outputs
• Includes 25.78125MHz, 128.90625 MHz and 161.1328125 MHz
for CMOS outputs
• Includes 25MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625
MHz for differential outputs
• Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz,
322.265625 MHz and 644.53125 MHz for differential outputs
• Provides IN1~IN6 input clock frequencies cover from 2 kHz to
156.25 MHz
• Supports Forced or Automatic operating mode switch controlled by
an internal state machine. It supports Free- Run, Locked and Hold-
over modes
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock fail-
ure
• Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
• Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and a 2
kHz or 8 kHz frame sync output signals
• Provides a 1PPS sync input signal and a 1PPS sync output signal
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,
ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 Recom-
mendations
OTHER FEATURES
• I2C and Serial microprocessor interface modes
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 72-pin QFN package, green package options available
APPLICATIONS
• 1 Gigabit Ethernet and 10 Gigabit Ethernet
• BITS / SSU
• SMC / SEC (SONET / SDH)
• DWDM cross-connect and transmission equipment
• Synchronous Ethernet equipment
• Central Office Timing Source and Distribution
• Core and access IP switches / routers
• Gigabit and Terabit IP switches / routers
• IP and ATM core switches and access equipment
• Cellular and WLL base-station node clocks
• Broadband and multi-service access equipment
The Short Form Datasheet presented herein represents a product currently in design or being considered for design. The noted characteristics are design targets. Integrated
Device Technologies, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2013 Integrated Device Technology, Inc.
1
February 4, 2013
DSC-7238/-
1 page  
IDT82V3396 SHORT FORM DATASHEET
DUAL SYNCHRONOUS ETHERNET LINE CARD PLL
2 PIN DESCRIPTION
Table 1: Pin Description
Name
OSCI
SONET/SDH
RST
EX_SYNC1
EX_SYNC2
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
IN3
IN4
IN5
IN6
FRSYN-
C_8K_1PPS
Pin No.
6
72
55
33
38
29
30
31
32
34
35
39
40
19
I/O Type
Description 1, 2
Global Control Signal
OSCI: Crystal Oscillator Master Clock
I CMOS A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
I
pull-up
CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
I
pull-down
I
pull-down
CMOS
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
I
I
I
pull-down
I
pull-down
I
pull-down
I
pull-down
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
PECL/LVDS
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
or 156.25 MHz is differentially input on this pair of pins. Whether the clock signal is PECL or
LVDS is automatically detected.
Single-ended input for differential input is also supported.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
A 2kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
PECL/LVDS
10 MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz,
or 156.25 MHz clock is differentially input on this pair of pins. Whether the clock signal is
PECL or LVDS is automatically detected.
Single-ended input for differential input is also supported.
CMOS
IN3: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
CMOS
IN4: Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
CMOS
IN5: Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
CMOS
IN6: Input Clock 6
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz, 6.48 MHz,
10 MHz, 19.44 MHz, 25 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz
or 156.25 MHz clock is input on this pin.
Output Frame Synchronization Signal
O
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
Pin Description
5 February 4, 2013
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IDT82V3396.PDF ] | |
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