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PDF IDT8T53S111I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T53S111I | |
| Descripción | 1:10 LVPECL Output Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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1:10 LVPECL Output Fanout Buffer
IDT8T53S111I
DATA SHEET
General Description
The IDT8T53S111I is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The IDT8T53S111I
is characterized to operate from a 3.3V and 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the IDT8T53S111I ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two selectable differential inputs and ten low skew outputs are
available. The integrated VREF voltage generator enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
• Ten low skew, low additive jitter LVPECL outputs
• Two selectable, differential LVPECL clock inputs
• Differential pairs can accept the following differential input
levels: LVDS, LVPECL and CML
• Maximum input clock frequency: 2.5GHz
• LVCMOS interface levels for the control input (input select)
• Output skew: 15ps (typical)
• Propagation delay: 250ps (typical)
• Additive phase jitter, RMS; fREF = 156.25MHz (12kHz - 20MHz):
30fs (typical)
• Full 3.3V and 2.5V supply voltage
• Maximum device current consumption (IEE): 126mA
• Lead-free (RoHS 6) 32-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
PCLK0
nPCLK0
Pulldown
PU / PD
PCLK1
nPCLK1
Pulldown
PU / PD
0
1
SEL
VREF
Pulldown
VOLTAGE
REFERENCE
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Pin Assignment
24 23 22 21 20 19 18 17
VCCO 25
16 VCCO
nQ2 26
15 Q7
Q2 27
14 nQ7
nQ1 28
13 Q8
Q1 29
12 nQ8
nQ0 30
11 Q9
Q0 31
10 nQ9
VCCO 32
9 VCCO
12 34 5 67 8
IDT8T53S111I
32-lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm E-Pad
NL Package, Top View
IDT8T53S111NLGI REVISION A JULY 12, 2012
1
©2012 Integrated Device Technology, Inc.
1 page  
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
2.5
tPD
tsk(o)
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 3
PCLK[0:1], nPCLK[0:1]
to any Q[0:9], nQ[0:9]
for VPP = 0.1V or 0.3V
196 250 300
15 50
tsk(i)
Input Skew; NOTE 3
5 25
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew;
NOTE 3, 4
fREF = 50MHz
14 38
17 115
Buffer Additive Phase
tJIT
Jitter, RMS; refer to
Additive Phase Jitter
fREF = 156.52MHz
Integration Range: 12kHz – 20MHz
Section
30 120
tR / tF
MUXISOLATION
VPP
Output Rise/ Fall Time
MUX Isolation; NOTE 5
Input Peak-to-Peak
Voltage; NOTE 5
20% to 80%
fREF = 100MHz
f 1.5GHz
f > 1.5GHz
50 90 160
-75
0.1 1.5
0.2 1.5
VCMR
Common Mode Input
Voltage; NOTE 6, 7
1.0 VCCO – 0.3
VO(PP)
Output Voltage Swing,
Peak-to-Peak
fREF 2GHz
0.5 0.65 0.8
VDIFF_OUT
Differential Output Voltage
Swing, Peak-to-Peak
fREF 2GHz
1.0 1.3 1.6
Units
GHz
ps
ps
ps
ps
ps
fs
ps
dB
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, temperature, frequency and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
NOTE 6: VIL should not be less than -0.3V.
NOTE 7: Common mode input voltage is defined as the crosspoint.
IDT8T53S111NLGI REVISION A JULY 12, 2012
5
©2012 Integrated Device Technology, Inc.
5 Page 
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 3A to 3E show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
CML
Zo = 50Ω
Zo = 50Ω
2.5V
R1 R2
50Ω 50Ω
2.5V
PCLK
nPCLK
LVPECL
Input
2.5V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
2.5V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
2.5V
LVPECL
Zo = 50Ω
Zo = 50Ω
2.5V
R3
250Ω
R4
250Ω
2.5V
PCLK
R1
62.5Ω
R2
62.5Ω
nPCLK
LVPECL
Input
2.5V
Zo = 50Ω
Zo = 50Ω
2.5V LVPECL Driv er
R6 R7
100Ω-180Ω 100Ω-180Ω
2.5V
R1
C1 100Ω
C2
R3
100Ω
PCLK
nPCLK
R2
100Ω
R4
100Ω
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
2.5V
LVDS
Zo = 50Ω
Zo = 50Ω
2.5V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 3E. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
IDT8T53S111NLGI REVISION A JULY 12, 2012
11
©2012 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet IDT8T53S111I.PDF ] | |
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