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PDF ISL22512 Data sheet ( Hoja de datos )
| Número de pieza | ISL22512 | |
| Descripción | Single Push Button Controlled Potentiometer | |
| Fabricantes | Intersil | |
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ISL22512
Single Push Button Controlled Potentiometer (XDCP™)
Data Sheet
October 12, 2015
FN6679.3
Low Noise, Low Power, 16 Taps, Push
Button Controlled Potentiometer
The Intersil ISL22512 is a three-terminal digitally-controlled
potentiometer (XDCP) implemented by a resistor array
composed of 15 resistive elements and a wiper switching
network. The ISL22512 features a push button control, a
shutdown mode, as well as an industry-leading µTQFN
package.
The push button control has individual PU and PD inputs for
adjusting the wiper. To eliminate redundancy, the wiper
position will automatically increment or decrement if one of
these inputs is held longer than one second.
Forcing both PU and PD low for more than two seconds
activates shutdown mode. Shutdown mode disconnects the
top of the resistor chain and moves the wiper to the lowest
position, minimizing power consumption.
The three terminals accessing the resistor chain naturally
configure the ISL22512 as a voltage divider. A rheostat is
easily formed by floating an end terminal or connecting it to
the wiper.
NC
VCC (SUPPLY VOLTAGE)
O
PU 1
9 VCC
PD 2 µTQFN 8 ASE
RH 3 (Top View) 7 RL
PU
RH VSS 4
6 RW
PD CBOLNOTCRKOL RW
NC
ASE
O
PU 1
8 VCC
RL PD 2 SOIC 7 ASE
RH 3 (Top View) 6 RL
VSS 4
5 RW
VSS (GROUND)
Features
• Solid-State Non-Volatile Potentiometer
• Push Button Controlled
• Single or Auto Increment/Decrement
- Fast Mode after 1s Button Press
• AUTOSTORE of Last Wiper Position or Manual Store of
Wiper Position
• Shutdown Mode
• 16 Wiper Tap Points
- Middle Scale Wiper Position on Power-Up
• Low Power CMOS
- VCC = 2.7V to 5.5V
- Terminal Voltage, 0 to VCC
- Standby Current, 3µA max
• RTOTAL Value = 10k
• High Reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T +55°C
• Packages
- 8 Ld SOIC
- 10 Ld µTQFN (2.1mmx1.6mm)
• Pb-Free (RoHS Compliant)
Applications
• Volume Control
• LED/LCD Brightness Control
• Contrast Control
• Programming Bias Voltages
• Ladder Networks
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 2008, 2009, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL22512
DC Electrical Specifications
Over recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN TYP MAX
(Note 18) (Note 5) (Note 18)
ICC VCC Active Current
VCC = 5.5V, perform wiper move
operation
150
ICC VCC Current During Store Operation
VCC = 5.5V, perform non-volatile
store operation
2
ISB
ILkg
VIH
VIL
CIN
(Note 17)
Standby Current
PU, PD Input Leakage Current
PU, PD Input HIGH Voltage
PU, PD input LOW Voltage
PU, PD Input Capacitance
0.6 3
VIN = VSS to VCC
-2 +2
VCC x 0.7
VCC x 0.1
VCC = 3.3V, TA = +25°C, f = 1MHz
10
Rpull_up Pull-Up Resistor for PU and PD
(Note 17)
1
EEPROM SPECIFICATIONS
EEPROM Endurance
1,000,000
EEPROM Retention
Temperature 55°C
50
UNIT
µA
mA
µA
µA
V
V
pF
M
Cycles
Years
AC Electrical Specifications
Over recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
MIN
(Note 18)
TYP
(Note 5)
MAX
(Note 18)
UNIT
tGAP
Time Between Two Separate Push Button Events
2
ms
tDB Debounce Time
15 28 ms
tS SLOW Wiper Change on a Slow Mode
100 250 390 ms
tS FAST Wiper Change on a Fast Mode
25 50 78 ms
tstdn Time to Enter Shutdown Mode (keep PU and PD LOW)
(Note 17)
2
s
tPU Power-Up to Wiper Stable
500 µs
tR VCC VCC Power-Up Rate
0.2 50 V/ms
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)15 – V(RW)0]/15. V(RW)31 and V(RW)0 are voltage on RW pin for the DCP register set to 0F hex and 00 hex respectively. LSB is
the incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)31 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB -1, for i = 1 to 15; i is the DCP register setting.
10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 15
11. TCV
=
-------M-----a----x------V-------R-----W--------i-----–-----M-----i--n------V-------R-----W--------i-------- ------1---0----6-------for i = 5 to 15 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
MaxVRWi + MinVRWi 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
12. MI = |RW15 – RW0|/15. MI is a minimum increment. RW15 and RW0 are the measured resistances for the DCP register set to 1F hex and 00
hex respectively.
13. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW15/MI, when measuring between RW and RH.
14. RDNL = (RWi – RWi-1)/MI, for i = 1 to 15.
15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 15.
16.
TCR
=
-------M-----a----x------R-----i-----–-----M-----i--n------R-----i--------
MaxRi + MinRi 2
------1---0----6-------
+ 165 °C
for i = 5 to 15, T
minimum value
= -40°C to +125°C. Max( ) is the maximum value
of the resistance over the temperature range.
of
the
resistance
and
Min
(
)
is
the
17. Limits should be considered typical and are not production tested.
18. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
5 FN6679.3
October 12, 2015
5 Page 
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
ISL22512
INDEX
AREA
1 23
TOP VIEW
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
0.50 (0.20)
0.25 (0.01)
x 45°
8°
0°
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
5.00 (0.197)
4.80 (0.189)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
11
2.20 (0.087)
SEATING PLANE
1.75 (0.069)
1.35 (0.053)
-C-
0.25(0.010)
0.10(0.004)
18
0.60 (0.023)
27
1.27 (0.050)
36
45
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6679.3
October 12, 2015
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL22512.PDF ] | |
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