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PDF SQS420EN Data sheet ( Hoja de datos )
| Número de pieza | SQS420EN | |
| Descripción | Automotive N-Channel MOSFET | |
| Fabricantes | Vishay | |
| Logotipo |  |
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SQS420EN
Vishay Siliconix
Automotive N-Channel 20 V (D-S) 175 °C MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω) at VGS = 4.5 V
RDS(on) (Ω) at VGS = 2.5 V
RDS(on) (Ω) at VGS = 1.8 V
ID (A)
Configuration
PowerPAK® 1212-8
20
0.0280
0.0320
0.0380
8
Single
D
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• AEC-Q101 Qualifiedd
• 100 % Rg and UIS Tested
• Compliant to RoHS Directive 2002/95/EC
3.30 mm
S
1S
3.30 mm
2
S
3G
4
D
8D
7
D
6
D
5
Bottom View
Part Marking Code: Q011
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
G
S
N-Channel MOSFET
PowerPAK 1212-8
SQS420EN-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Currenta
Continuous Source Current (Diode Conduction)a
Pulsed Drain Currentb
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
Maximum Power Dissipationb
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)e, f
TC = 25 °C
TC = 125 °C
L = 0.1 mH
TC = 25 °C
TC = 125 °C
VDS
VGS
ID
IS
IDM
IAS
EAS
PD
TJ, Tstg
LIMIT
20
±8
8
8
8
32
10
5
18
6
- 55 to + 175
260
UNIT
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
LIMIT
UNIT
Junction-to-Ambient
Junction-to-Case (Drain)
PCB Mountc
RthJA
81
°C/W
RthJC
8.1
Notes
a. Package limited.
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
c. When mounted on 1" square PCB (FR4 material).
d. Parametric verification ongoing.
e. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
f. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S11-2129 Rev. B, 31-Oct-11
1
Document Number: 67067
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
www.vishay.com
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
IDM Limited
10 Limited by RDS(on)*
1 ID Limited
100 μs
1 ms
10 ms
100 ms
1 s,10 s,DC
1
Duty Cycle = 0.5
0.1
TC = 25 °C
Single Pulse
0.01
0.01
BVDSS Limited
0.1 1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
SQS420EN
Vishay Siliconix
0.2
0.1
0.1
0.05
0.02
0.01
10-4
Notes:
PDM
Single Pulse
10-3
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 81 °C/W
3. TJM - TA = PDMZthJA(t)
4. Surface Mounted
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100 1000
Normalized Thermal Transient Impedance, Junction-to-Ambient
S11-2129 Rev. B, 31-Oct-11
5
Document Number: 67067
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
Configuration
SO-8
Single Dual
TSSOP-8
Single Dual
TSOP-8
Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90
PPAK 1212
Single Dual
2.4 5.5
PPAK SO-8
Single Dual
1.8 5.5
PowerPAK 1212
49.8 °C
Standard SO-8
85 °C
Standard TSSOP-8
149 °C
TSOP-6
125 °C
2.4 °C/W
PC Board at 45 °C
20 °C/W
52 °C/W
Figure 4. Temperature of Devices on a PC Board
40 °C/W
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction to- foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
By minimizing the junction-to-foot thermal resistance, the
MOSFET die temperature is very close to the tempera-
ture of the PC board. Consider four devices mounted on
a PC board with a board temperature of 45 °C (Figure 4).
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.
Designers add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It
is helpful to have some information about the thermal
performance for a given area of spreading copper.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
cations. The top layer was cut back to a smaller area and
at each step junction-to-ambient thermal resistance
measurements were taken. The results indicate that an
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Document Number 71681
03-Mar-06
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