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PDF CMX7045 Data sheet ( Hoja de datos )
| Número de pieza | CMX7045 | |
| Descripción | AIS SART Processor | |
| Fabricantes | Consumer Microcircuits Limited | |
| Logotipo |  |
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CML Microcircuits
CMX7045
AIS SART ProcessorCOMMUNICATION SEMICONDUCTORS
D/7045FI-1.x/4 February 2013
DATASHEET
Advance Information
7045FI-1.x Marine AIS SART Processor
Features:
Tx AIS GMSK Modem
AIS SART Formatted Data
Battery Monitor
Flexible Tx Interface
Configurable by Function Image™
Two Auxiliary Clock Generators
Two-Input Auxiliary (10-bit) ADC
Four Auxiliary (10-bit) DACs
Conforms to IEC 61097-14
Integration Roadmap
Low-Power (3.0V to 3.6V) Operation
Low Profile 48-pin LQFP or VQFN
2-Point or I/Q Modulation
Applications:
Automatic Identification System (AIS) Search
And Rescue (SART) for Marine Safety
Man Overboard (MOB) maritime survivor
location device
Personal Locator Beacon (PLB) tracking
transmitter
PLL
VCO
C-BUS
µC
PA PA Ramp
Ref
Osc
Tx Enable
Slot Clock
CMX7045
SART
Processor
Monitor
SART Test
SART Active
GPS Lock
Strobe
RTC
GPS
Switched
mode PSU
Battery
This document contains:
Datasheet
User
Manual
1 Brief Description
The CMX7045 is a dedicated processor for marine Automatic Identification System (AIS), Search and
Rescue Transmitter (SART) operation, fully meeting the requirements of IEC 61097-14.
This highly integrated and flexible device includes a 9600 baud GMSK modem for transmission of
formatted data. Additional auxiliary functions are also provided to further support the system host, these
include: a two-input 10-bit Auxiliary ADC, four 10-bit Auxiliary DACs, two system clock outputs and four
GPIOs.
The CMX7045 offers low power sleep modes to ensure maximum system battery life and is available in a
in a small 48-pin LQFP or VQFN package.
This Datasheet is the first part of a two-part document comprising Datasheet and User Manual: the User
Manual can be obtained by registering your interest in this product with your local CML representative.
2013 CML Microsystems Plc
1 page  
Marine AIS SART Processor
2 Block Diagram
Transmit Functions
Buffer
HDLC
Encode
NRZI
Encode
GMSK
Modulation
DAC1
DAC2
DAC3
DAC4
ADC1
ADC2
Auxiliary 10-bit DACs
DAC 1
DAC 2
DAC 3
DAC 4
Ramp Profile RAM
Multiplexed 10-bit ADC
MUX
ADC
Auxiliary Functions
Configurable GPIO
GPIO
Programmable System Clocks
System Clock 1
System Clock 2
AVDD
VBIAS
AVSS
DVDD
VDEC
DVSS
System Control
Bias
Reg
Main Clock
Digital PLL
Registers
Power Control
Internal Systems
Control
Crystal
Oscillator
C-BUS
Interface
Figure 1 Block Diagram
CMX7045
MOD1
MOD2
TXENA
SLOTCLK
CS-SYNC
SLTCLKOP
SYSCLK1
SYSCLK2
XTAL/CLK
XTALN
IRQN
RDATA
CSN
CDATA
SCLK
2013 CML Microsystems Plc
5
D/7045FI-1.x/4
5 Page 
Marine AIS SART Processor
CMX7045
6 General Description
6.1 Overview
Tx Modem Functions
AIS 25kHz channel (GMSK, 9600bps, 2.4kHz deviation, BT = 0.4)
AIS Burst mode with full AIS frame formatting (HDLC-type)
o Bit stuffing
o NRZI coding
o Training sequence and start/stop flag insertion
o CRC generation
AIS Raw mode (for greater flexibility)
o Supports arbitrary data streams for user-defined protocols
160-byte (equivalent to 5 AIS slots) Tx Data Buffer
Flexible Tx Interface
o Two-point modulation outputs, with independent gain and polarity controls
Analogue I/O Functions
Auxiliary ADC system
o A two-input 10-bit successive approximation ADC with integrated sample and hold
AuxADC1-2
Auxiliary DAC system
o Four general purpose auxiliary 10-bit DACs, AuxDAC1-4
Ramping auxiliary DAC, RAMDAC (using AuxDAC1)
o RAMDAC steps through a user-configured sequence of DAC output values to develop a
specific rising/falling output signal. This is useful for ramping an RF PA, and can be
configured to operate automatically at the start and end of a burst.
System Functions
All internal subsystems are controlled via a single serial host interface to reduce host µC pin count
and simplify external host driver complexity.
Transaction oriented command/response logical host interface executes tasks supporting normal
operation, device configuration, and functions to assist manufacturing calibration trimming of
external circuits.
Internal system clock derived from reference oscillator and eliminates the need for additional
XTAL or baseband clock oscillator.
System Clock Synthesisers generate two clocks for external use to support peripheral devices.
Function Image™ is loaded directly from the host µC via C-BUS.
Integrated 2.5V regulator can develop 2.5V from required 3.3V supply.
Powersave facilities minimise total system power.
6.2 AIS System Formats
The AIS system uses two basic channel access mechanisms: Self Organising Time Division Multiple
Access (SOTDMA) and Carrier-Sensing Time Division Multiple Access (CSTDMA). The CMX7045 is
compatible with both systems and offers additional features which simplify the implementation of an AIS
SART device conforming to IEC 61097-14.
The relevant International standards are:
[0] ITU-R M.1371-4
[1] IEC 61993-2 Class A
[2] IEC 62287-1 Class B CSTDMA
[3] IEC 62287-2 Class B SOTDMA
[4] IEC 62320-1 Base Station
[5] IEC 62320-2 Aids to Navigation
[6] IEC 61097-14 AIS-SART
2013 CML Microsystems Plc
11
D/7045FI-1.x/4
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CMX7045.PDF ] | |
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