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PDF NPIC6C4894 Data sheet ( Hoja de datos )
| Número de pieza | NPIC6C4894 | |
| Descripción | Power logic 12-bit shift register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
Rev. 1 — 17 April 2014
Product data sheet
1. General description
The NPIC6C4894 is a 12-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input (D) to the parallel open-drain outputs
(QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each
shift register stage is transferred to the storage register when the latch enable (LE) input is
HIGH. Data in the storage register drives the gate of the output extended-drain NMOS
transistor whenever the output enable input (OE) is HIGH. A LOW on OE causes the
outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect
the state of the registers. Two serial outputs (QS1 and QS2) are available for cascading a
number of NIC6C4894 devices. Serial data is available at QS1 on positive-going clock
edges to allow high-speed operation in cascaded systems with a fast clock rise time. The
same serial data is available at QS2 on the next negative going clock edge. It is used for
cascading NPIC6C4894 devices when the clock has a slow rise time. The open-drain
outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed
for use in systems that require moderate load power such as LEDs. Integrated voltage
clamps in the outputs, provide protection against inductive transients. This protection
makes the device suitable for power driver applications such as relays, solenoids and
other low-current or medium-voltage loads.
2. Features and benefits
Specified from 40 C to +125 C
Low RDSon
12 Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Low power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
HBM JS-2011 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V
1 page  
NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
7. Functional description
Table 3. Function table[1]
At the positive clock edge, the information in the 10th register stage is transferred to the 11th register stage and the QS output
Control
Input
Parallel output
Serial output
CP OE LE D
QP0
QPn
QS1[2]
QS2[3]
L
X
X
Z
Z
Q10S
no change
L X X Z Z no change Q11S
HL
X
no change no change Q10S
no change
H
H
L
Z
QPn1
Q10S
no change
HHHL
QPn1
Q10S
no change
H H H no change no change no change Q11S
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition;
Z = high-impedance OFF-state.
[2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
[3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
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VHULDO46
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VHULDO46
RXWSXW
Fig 7. Timing diagram
DDD
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 21
5 Page 
NXP Semiconductors
NPIC6C4894
Power logic 12-bit shift register; open-drain outputs
9,
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*1'
9,
/(LQSXW
*1'
9
43QRXWSXW
92/
90
90
W:
W3/=
9;
W3=/
9<
DDD
Measurement points are given in Table 8.
VOL is the typical output voltage level that occurs with the output load.
Fig 11. Latch enable (LE) to output (QPn) propagation delays and the latch enable pulse width
9,
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*1'
9
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90
W3/=
RXWSXWV
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9;
W7/+
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GLVDEOHG
W3=/
9<
9;
W7+/
RXWSXWV
HQDEOHG
DDD
Measurement points are given in Table 8.
VOL is the typical output voltage level that occurs with the output load.
Fig 12. Output enable (OE) to output (QPn) and output transition time
NPIC6C4894
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 21
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