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PDF STLC4560 Data sheet ( Hoja de datos )
| Número de pieza | STLC4560 | |
| Descripción | Single chip 802.11b/g WLAN radio | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de STLC4560 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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STLC4560
Single chip 802.11b/g WLAN radio
Data Brief
Features
■ Extremely small footprint
■ Ultra low power consumption
■ Fully compliant with the IEEE 802.11b and
802.11g WLAN standards
■ Support for 54, 48, 36, 24, 18, 12, 9, and
6 Mbit/s OFDM, 11 and 5.5 Mbit/s CCK and
legacy 2 and 1 Mbit/s data rates
■ Single chip 802.11b/g WLAN solution with fully
integrated:
– zero IF (ZIF) transceiver
– voltage controlled oscillator (VCO)
– high-speed A/D and D/A converters
– OFDM and CCK baseband processor
– ARM9 media access controller (MAC)
– Mode selectable SPI or SDIO host interface
(up to 48 Mbps)
– passive components integration
– PA bias control
– flexible integrated power management unit
– glueless FEM interface
■ Intelligent power control, including 802.11
power save mode
■ Fully integrated Bluetooth coexistence
Applications
■ Cellular phones
■ Personal digital assistants (PDA)
■ Portable computers
■ Hand-held data transfer devices
■ Cameras
■ Computer peripherals
■ Cable replacement
LFBGA240 (8.5x8x1.4mm)
Description
The STLC4560 is a single chip 802.11b/g WLAN
radio for embedded, low-power and very small
form factor mobile applications. The product
conforms to the IEEE 802.11b and 802.11g
protocols operating in the 2.45 GHz ISM
frequency band supporting OFDM data rates of
54, 48, 36, 24, 18, 12, 9, and 6 Mbit/s as well as
CCK data rates of 11 and 5.5 Mbit/s and legacy
data rates of 2 and 1 Mbit/s.
The STLC4560 is a fully integrated wireless radio
including a ZIF transceiver, RF Synthesizer/VCO,
high-speed data converters, an OFDM/CCK
digital baseband processor, an ARM9-based
MAC and a complete power management unit
with integrated PA bias control. In addition some
passive components are integrated further
reducing the overall reference design cost and
size. An external FEM completes a highly
integrated chip set solution.
Host control is provided by a flexible SPI or SDIO
serial interface. The SPI interface supports a
maximum clock rate of 48 MHz whereas the 4-bit
SDIO supports a maximum clock rate of 25 MHz.
For maximum flexibility, the STLC4560 accepts
system reference clock frequencies of 19.2, 26,
38.4 and 40 MHz. A reference design evaluation
platform of hardware and software is provided to
system integrators to rapidly enable wireless
connectivity to mobile platforms.
January 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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www.st.com
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STLC4560
3 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet STLC4560.PDF ] | |
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