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PDF 74ALVCH16244 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVCH16244 | |
| Descripción | Low-Voltage 16-Bit Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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74ALVCH16244
Low−Voltage 16−Bit Buffer
with Bus Hold 1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16244 is an advanced performance, non−inverting
16−bit buffer. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
The 74ALVCH16244 is nibble controlled with each nibble
functioning identically, but independently. The control pins may be
tied together to obtain full 16−bit operation. The 3−state outputs are
controlled by an Output Enable (OEn) input for each nibble. When
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are
in the high impedance state. The data inputs include active bushold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: VCC = 1.65 − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.0 ns max for 3.0 to 3.6 V
3.7 ns max for 2.3 to 2.7 V
6.0 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16244
http://onsemi.com
MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVCH16244DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
74ALVCH16244DTR TSSOP 2500/Tape & Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 2
1
Publication Order Number:
74ALVCH16244/D
1 page  
74ALVCH16244
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
TA = −40°C to +85°C
VCC = 3.0 V to 3.6 V VCC = 2.3 V to 2.7 V VCC = 1.65 V − 1.95 V
Symbol
Parameter
Waveform Min Max Min Max Min
Max Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tOSHL
tOSLH
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 11)
1
2
2
1.0 3.0 1.0 3.7
1.0 3.0 1.0 3.7
1.0
1.0
6.0 ns
6.0
1.0 4.4 1.0 5.7
1.0 4.4 1.0 5.7
1.0
1.0
8.2 ns
8.2
1.0 4.1 1.0 5.2
1.0 4.1 1.0 5.2
1.0
1.0
6.8 ns
6.8
0.5 0.5
0.5 0.5
0.75 ns
0.75
10. For CL = 50 pF, add approximately 300 ps to the AC maximum specification.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
COUT
Output Capacitance
CPD Power Dissipation Capacitance
12. VCC = 1.8, 2.5 or 3.3 V; VI = 0 4 V or VCC.
Condition
Note 12
Note 12
Note 12, 10 MHz
Typical
6
7
20
Unit
pF
pF
pF
Dn Vm
tPLH
On
Vm
Vm
tPHL
Vm
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
OEn
tPZH
On
tPZL
On
Vm
tPHZ
Vm
tPLZ
Vm
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 4. AC Waveforms
VIH
0V
VOH
VOL
VIH
0V
VOH
Vy
≈0V
≈ VCC
Vx
VOL
http://onsemi.com
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ALVCH16244.PDF ] | |
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