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PDF STK672-540 Data sheet ( Hoja de datos )
| Número de pieza | STK672-540 | |
| Descripción | Two-Phase Stepping Motor Driver | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA0754A
STK672-540
Thick-Film Hybrid IC
2-phase Stepping Motor Driver
http://onsemi.com
Overview
The STK672-540 is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
• Office photocopiers, printers, etc.
Features
• The motor speed can be controlled by the frequency of an external clock signal.
• 2-phase excitation or 1-2 phase excitation is selected according to switching the state of the MODE pin (low or high).
• The phase is maintained even if the excitation mode is switched in the middle of operation.
• The direction of rotation can be changed by applying a high or low signal to the CWB pin used to select the direction
of rotation.
• Supports schmitt input for 2.5V high level input.
• Incorporating a current detection resistor (0.11Ω: resistor tolerance ±2%), motor current can be set using two external
resistors.
• Equipped with an ENABLE pin that, during clock input, allows motor output to be cut-off and resumed later while
maintaining the same excitation timing.
Semiconductor Components Industries, LLC, 2013
June, 2013
62911HKPC 018-08-0038/71608HKIM No. A0754-1/22
1 page  
Precautions
STK672-540
[GND wiring]
• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 1 of the hybrid IC. Also, the GND side of RO2 must be directly wired from P.GND terminal Pin 1 in order to
accurately set the current.
[Input pins]
• Insert resistor RO3 (47 to 100Ω) so that the discharge energy from capacitor CO2 is not directly applied to the CMOS
IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6V (when If = 0.1A),
this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without
problem.
• Apply 2.5V High level input to pins 8, 9, 10, 11, and 12.
• If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to P.GND,
Pin 1, and do not apply a voltage greater than or equal to VDD voltage.
• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 8, 9, 10, 11, and 12 are
used as inputs, a 10 to 47kΩ pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.6V at Low level.
• To prevent malfunction due to chopping noise, we recommend that you mount a 1000pF capacitor between Pin 1 and
each of the input Pins 8, 9, 10, 11, and 12. Be sure to mount the capacitor as close as possible to the pins of hybrid IC.
If input is fixed Low, directly connect to Pin 1.
If input is fixed High, directly connect to the 5V power line.
[Current setting Vref]
• In consideration of the specifications of the Vref input bias current, IIB, a resistance from several kΩ to 100kΩ is
recommended for RO1.
• If the motor current is temporarily reduced, the circuit given below (STK672-540: IOH>0.25A) is recommended.
• Although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection
function to ensure that the current does not exceed the maximum output current, IOH max. If Vref is mistakenly set to
a voltage that exceeds IOH max, the driver will be damaged by overcurrent.
5V
RO1
Vref
R3 RO2
5V
RO1
Vref
R3
RO2
No. A0754-5/22
5 Page 
Usage Notes
STK672-540
1. STK672-530 and STK672-540 input signal functions and timing
(All inputs have no internal pull-up resistor.)
[RESETB and CLOCK (Input signal timing when power is first applied)]
As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the
F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10μs, as shown below.
The capacitor CO2, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the
RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application
must have the timing shown in figure.
Rise of the 5V supply
voltage
RESETB signal input
CLOCK signal
At least 10μs
At least 5μs
Figure 1 RESETB and CLOCK Signals Input Timing
[CLOCK (Phase switching clock)]
• Input frequency: DC to 50kHz
• Minimum pulse width: 10μs
• Signals are read on the rising edge.
[CWB (Motor direction setting)]
The direction of rotation is switched by setting CWB to 1 (high) or 0 (low).
See the timing charts for details on the operation of the outputs.
Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of
the CLOCK input.
[ENABLE (Controls forced OFF for A, AB, B, and selects BB and selects operation/hold mode of the hybrid IC)]
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later
restored to the 1 state, the IC will resume operation with the excitation timing continued from before
the point ENABLE was set to 0.
Enable must be initially set high for input as shown in the timing chart.
[MODE (Excitation mode selection)]
MODE=0: 2-phase excitation
MODE=1: 1-2 phase excitation
See the timing charts for details on output operation in these modes.
Note: The state of the MODE input must not be changed during the 5μs period before and after the rising edge of the
CLOCK input.
No. A0754-11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet STK672-540.PDF ] | |
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