AD9154 Datasheet PDF - Analog Devices
| Part Number | AD9154 | |
| Description | Digital-to-Analog Converter | |
| Manufacturers | Analog Devices | |
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Data Sheet
Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
AD9154
FEATURES
Supports input data rates up to 1 GSPS
Proprietary, low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at
180 MHz IF
Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at
180 MHz IF
SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Input signal power detection
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Digital quadrature modulation using a numerically
controlled oscillator (NCO)
Nyquist band selection—mix mode
Selectable 1×, 2×, 4×, and 8× interpolation filters
Low power: 2.11 W at 1.6 GSPS, full operating conditions
88-lead, exposed pad LFCSP
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radio
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9154 is a quad, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate
of 2.4 GSPS, permitting multicarrier generation up to the Nyquist
frequency in baseband mode. The AD9154 includes features
optimized for direct conversion transmit applications, including
complex digital modulation, input signal power detection, and
gain, phase, and offset compensation. The DAC outputs are
optimized to interface seamlessly with the ADRF6720-27 radio
frequency quadrature modulator (AQM) from Analog Devices,
Inc. In mix mode, the AD9154 DAC can reconstruct carriers in
the second and third Nyquist zones. A serial port interface (SPI)
provides the programming/readback of internal parameters.
The full-scale output current can be programmed over a range
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT
0°/90° PHASE
SHIFTER
LPF
DAC
JESD204B
SYNCOUTx±
SYSREF
LO_IN
MOD_SPI
QUAD MOD
ADRF6720-27
QUAD DAC
DAC
RF
OUTPUT 1
0°/90° PHASE
SHIFTER
LPF
LO_IN
DAC
AD9154
MOD_SPI
DAC DAC
CLOCK SPI
Figure 1.
JESD204B
SYNCOUTx±
of 4 mA to 20 mA. The AD9154 is available in two different
88-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1. Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization.
4. Small package size with a 12 mm × 12 mm footprint.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD9154
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
Offset Error1
I/Q Gain Mismatch
Full-Scale Output Current
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Full-Scale Current DAC Monotonicity
MAIN DAC TEMPERATURE DRIFT
Gain2
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12
CVDD12
DIGITAL SUPPLY VOLTAGES
SIOVDD33
VTT
DVDD12
SVDD12
IOVDD
POWER CONSUMPTION
2× Interpolation Mode, JESD204B
Mode 4, Dual Link, 8 SERDES Lanes
AVDD33
PVDD12
CVDD12
SVDD12
DVDD12
SIOVDD33 + IOVDD
Test Conditions/Comments
With internal reference
Based on a 4 kΩ external resistor between I120 and ground
5%
5%
2%
5%
2%
5%
5%
2%
5%
2%
5%
fDAC = 1.6 GSPS, NCO on, IFOUT = 40 MHz, PLL on, DAC
full-scale current = 20 mA
Includes VTT
Min
−8.0
−3.0
19.9
3.9
2.0
3.13
1.14
1.274
1.14
1.274
3.13
1.1
1.14
1.274
1.14
1.274
1.71
Typ Max
16
±4.3
±8.2
−3.01
2322
+0.54
+8.0
+3.0
20.85
4.17
2.8
15
3.0
Guaranteed
21.3
4.4
3.37
−114
1.2
3.3 3.47
1.2 1.26
1.3 1.326
1.2 1.26
1.3 1.326
3.3 3.47
1.2 1.37
1.2 1.26
1.3 1.326
1.2 1.26
1.3 1.326
1.8 3.47
2.11
159
152
355
541.9
264.5
10.6
2.63
185
174
397
682
442
11.4
Unit
Bits
LSB
LSB
% FSR
ppm
% FSR
mA
mA
V
MΩ
pF
ppm/°C
V
V
V
V
V
V
V
V
V
V
V
V
V
W
mA
mA
mA
mA
mA
mA
1 Offset error is a measure of how far from full-scale range (FSR) the DAC output current is at 25°C (in ppm).
2 Gain drift is a measure of the slope of the DAC output current across its full temperature range (in ppm/°C).
Rev. B | Page 5 of 124
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