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PDF ADP1055 Data sheet ( Hoja de datos )
| Número de pieza | ADP1055 | |
| Descripción | Digital Controller | |
| Fabricantes | Analog Devices | |
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Data Sheet
Digital Controller for Power Supply
Applications with PMBus Interface
ADP1055
FEATURES
−40°C to +125°C operation
PMBus Revision 1.2 compliant with PEC and extended
manufacturer specific commands
32-bit password protection with command masking
64 address selections (16 base addresses, expandable to 64)
6 PWM control signals, 625 ps resolution
Frequency from 48 kHz to 1 MHz
Duty cycle double update rate
Digital control loop (PID + additional pole or zero
configurability)
Programmable loop filters (CCM, DCM, low/normal
temperature)
Fast line voltage feedforward
Adaptive dead time compensation for improved efficiency
Remote voltage sense
Redundant programmable OVP
Current sense
Primary side cycle-by-cycle fast protection
Secondary side cycle-by-cycle fast overcurrent protection
Secondary side averaged reverse current protection using
diode emulation mode with fixed debounce
Synchronous rectifier control for improved efficiency
in light load mode
Nonlinear gain for faster transient response from DCM to CCM
Frequency synchronization
Soft start and soft stop functionality
Average and peak constant current mode
External PN junction temperature sensing
4 GPIOs (2 GPIOs configurable as active clamp snubber PWMs)
Extended black box data recorder for fault recording
User trimming on input and output voltages and currents
Digital current sharing
APPLICATIONS
Isolated dc-to-dc power supplies and modules
Redundant power supply systems
GENERAL DESCRIPTION
The ADP1055 is a flexible, feature-rich digital secondary side
controller that targets ac-to-dc and isolated dc-to-dc secondary
side applications. The ADP1055 is optimized for minimal
component count, maximum flexibility, and minimum design
time. Features include differential remote voltage sense, primary
and secondary side current sense, pulse-width modulation (PWM)
generation, frequency synchronization, redundant OVP, and
current sharing. The control loop digital filter and compensation
terms are integrated and can be programmed over the PMBus™
interface. Programmable protection features include
overcurrent (OCP), overvoltage (OVP) limiting, undervoltage
lockout (UVLO), and external overtemperature (OTP).
The built-in EEPROM provides extensive programming of the
integrated loop filter, PWM signal timing, inrush current, and
soft start timing and sequencing. Reliability is improved through
a built-in checksum and programmable protection circuits.
A comprehensive GUI is provided for easy design of loop filter
characteristics and programming of the safety features. The
industry-standard PMBus provides access to the many monitoring
and system test functions. The ADP1055 is available in a 32-lead
LFCSP and operates from a single 3.3 V supply.
TYPICAL APPLICATION DIAGRAM
DC
INPUT
VOUT
LOAD
DRIVER
iCoupler ®
DRIVER
SR1 SR2
CS1
OUTA
OUTB
OUTC
OUTD
VFF
CS2– CS2+
ADP1055
RES ADD JTD JRTN GPIO1 TO GPIO4 CTRL SMBALRT
OVP
SDA SCL
VS+ VS–
ISHARE
SYNC
NC
VCORE
VDD AGND DGND
VDD
Figure 1.
PMBus
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADP1055
SPECIFICATIONS
VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range.
Table 1.
Parameter
SUPPLY
Supply Voltage
Supply Current
POWER-ON RESET
Power-On Reset
Undervoltage Lockout
Overvoltage Lockout
OVLO Debounce
VCORE PIN
Power-On Reset (POR)
Output Voltage
Maximum Time from POR to
Outputs Switching
OSCILLATOR AND PLL
PLL Frequency
OUTA, OUTB, OUTC, OUTD, SR1,
SR2 PINS
Output Low Voltage
Output High Voltage
Rise Time
Fall Time
VOLTAGE FEEDFORWARD (VFF PIN)
ADC Clock Frequency
Feedforward (Slow) Input
Voltage Range
ADC Usable Input Voltage Range
Measurement Accuracy (Slow
and Fast Feedforward)
Leakage Current
FEEDFORWARD FUNCTION
(VFF PIN)
Feedforward (Fast) Input
Voltage Range
Sampling Period for
Feedforward (Fast) ADC
VS LOW SPEED ADC
Input Voltage Range
Usable Input Voltage Range
ADC Clock Frequency
Symbol
VDD
IDD
POR
UVLO
OVLO
VOL
VOH
VFF
Test Conditions/Comments
4.7 μF capacitor connected to AGND
Normal operation (CTRL pin is high)
Normal operation (CTRL pin is low)
During EEPROM programming (40 ms)
During black box write
Current with VDD < VCORE POR
VDD rising
VDD falling
Set to 2 μs (Register 0xFE4D[5] = 0)
Set to 500 μs (Register 0xFE4D[5] = 1)
0.33 μF capacitor connected to DGND
VDD falling
TA = 25°C
No black box recording
(Register 0xFE48[1:0] = 00)
With black box recording
(Register 0xFE48[1:0] = 01, 10, or 11)
RES = 10 kΩ (±0.1%)
Sink current = 10 mA
Source current = 10 mA
CLOAD = 50 pF
CLOAD = 50 pF
For reporting; equivalent resolution
of 12 bits
Factory trimmed at 1.0 V
0% to 100% of usable input voltage range
10% to 90% of usable input voltage range
900 mV to 1.1 V
Equivalent resolution of 12 bits
Differential voltage from VS+ to VS−
Min Typ
3.0 3.3
63
55
IDD + 8
IDD + 8
100
2.75 2.85
3.8 4.0
2.0
500
2.1
2.6
10
45
190 200
VDD − 0.8
3.5
1.5
1.56
01
0
−2.5
−2.0
−1.5
0.6 1
1
01
0
1.56
Rev. A | Page 5 of 140
Max
3.6
3.0
2.97
4.1
210
0.8
1.6
1.57
+2.5
+2.0
+1.5
1.0
1.6
1.6
1.55
Unit
V
mA
mA
mA
mA
μA
V
V
V
μs
μs
V
V
ms
ms
MHz
V
V
ns
ns
MHz
V
V
% FSR
% FSR
% FSR
μA
V
μs
V
V
MHz
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP1055
OVP 1
VS+ 2
VS– 3
CS2+ 4
CS2– 5
NC 6
VFF 7
CS1 8
ADP1055
TOP VIEW
(Not to Scale)
24 ISHARE
23 SMBALRT
22 SDA
21 SCL
20 CTRL
19 GPIO1
18 GPIO2
17 GPIO3
NOTES
1. NC = NO CONNECT. LEAVE THIS PIN UNCONNECTED.
2. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT
THE EXPOSED PAD ON THE UNDERSIDE OF THE PACKAGE BE
SOLDERED TO THE PCB AGND PLANE.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 OVP Overvoltage Protection. This signal is referenced to AGND and is used for redundant OVP protection. The nominal
voltage at this pin should be 1 V. If this pin is not used, connect it to AGND.
2 VS+ Noninverting Voltage Sense Input. This signal is referenced to VS−. The nominal input voltage at this pin is 1 V. The
resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. This pin is
the input to the high frequency flash ADC.
3 VS− Inverting Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider on this input
must have a tolerance specification of 0.5% or better to allow for trimming. To reduce common-mode noise, connect
a 0.1 μF capacitor from VS− to AGND.
4
CS2+
Noninverting Differential Current Sense Input. This signal is referenced to CS2−. If this pin is not used, connect it to
AGND.
5
CS2−
Inverting Differential Current Sense Input. If this pin is not used, connect it to AGND. This pin must have a low
ohmic connection to AGND thought the sense resistor.
6 NC
No Connect. Leave this pin unconnected.
7 VFF
Voltage Feedforward. Two optional functions can be implemented using this pin: feedforward and input voltage
loss detection. This pin is typically connected upstream of the output inductor through a resistor divider network
in an isolated converter. The nominal voltage at this pin should be 1 V. This signal is referenced to AGND. If this pin
is not used, connect it to AGND.
8 CS1 Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the fast
OCP comparator. This signal is referenced to PGND. The resistors on this input must have a tolerance specification
of 0.5% or better to allow for trimming. If this pin is not used, connect it to AGND.
9 SR1
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referenced to AGND.
10 SR2
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referenced to AGND.
11 OUTA PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
12 OUTB PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
13 OUTC PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
14
OUTD
PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
15 SYNC Synchronization Input Signal. This pin is used as a reference for the internal PWM frequency. This signal is
referenced to AGND and must have a nominal duty cycle of 50%. If this pin is not used, connect it to AGND and
program Register 0xFE55[6] = 1.
16
GPIO4
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND. This pin can also be
configured as an active snubber PWM output.
17
GPIO3
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND. This pin can also be
configured as an active snubber PWM output.
Rev. A | Page 11 of 140
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP1055.PDF ] | |
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