M2V64S30BTP-10L Datasheet PDF - Mitsubishi
| Part Number | M2V64S30BTP-10L | |
| Description | 64M bit Synchronous DRAM | |
| Manufacturers | Mitsubishi | |
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SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
DESCRIPTION
The M2V64S20BTP is organized as 4-bank x 4194304-word x 4-bit, M2V64S30BTP is
organized as 4-bank x 2097152-word x 8-bit, and M2V64S40BTP is organized as 4-bank x
1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The M2V64S20BTP, M2V64S30BTP, M2V64S40BTP
achieve very high speed data rate up to 125MHz, and are suitable for main memory or
graphic memory in computer systems.
FEATURES
- Single 3.3v ± 0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9 (x4), A0-A8(x8), A0-A7(x16)
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
M2V64S20BTP
M2V64S30BTP
M2V64S40BTP
-7, -7L
-8, -8L
-8A
-10, -10L
Max.
Frequency
CLK Access
Time
100MHz(CL2)
6ns
100MHz(CL3)
6ns
125MHz
6ns
100MHz
8ns
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.2)
Apr. '99
64M bit Synchronous DRAM
MITSUBISHI LSIs
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
BASIC FUNCTIONS
The M2V64S20(30,40)BTP provides basic functions, bank (row) activate, burst read / write,
bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the
command truth table.
CLK
/CS Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command define basic commands
/WE
Command
CKE
Refresh Option @refresh command
A10 Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after the
burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, both banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated inter-nally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M2V64S30BTP-10L electronic component. |
| Information | Total 30 Pages | |
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| Download | [ M2V64S30BTP-10L.PDF Datasheet ] | |
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