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PDF 844002 Data sheet ( Hoja de datos )
| Número de pieza | 844002 | |
| Descripción | Crystal-to-LVDS Frequency Synthesizer | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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FemtoClock® Crystal-to-LVDS
Frequency Synthesizer
844002
DATASHEET
GENERAL DESCRIPTION
The 844002 is a 2 output LVDS Synthesizer optimized to generate
Fibre Channel reference clock frequencies. Using a 26.5625MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz.
The 844002 uses IDT’s 3rd generation low phase noise VCO
technology and can achieve <1ps typical rms phase jitter, easily
meeting Fibre Channel jitter requirements.The 844002 is packaged
in a small 20-pin TSSOP package.
FEATURES
• Two LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
23.4375
Inputs
F_SEL1
F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
0 0 24
3
0 1 24
4
1 0 24
6
1 1 24 12
0 0 24
3
8
6
4
2
8
Output
Frequency
(MHz)
212.5 (default)
159.375
106.25
53.125
187.5 (default)
BLOCK DIAGRAM
Pulldown
F_SEL[1:0]
nPLL_SEL Pulldown
REF_CLK Pulldown
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
PIN ASSIGNMENT
844002
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
Q0
nQ0
Q1
nQ1
M = 24 (fixed)
MR Pulldown
844002 REVISION B 6/9/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
844002 DATA SHEET
TABLE 5A. AC CHARACTERISTICS, V = V = 3.3V±5%, TA = 0°C TO 70°C
DD DDO
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f Output Frequency
OUT
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
0.65
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz - 10MHz)
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
0.61
0.74
0.64
187.5MHz, (637kHz - 10MHz)
0.80
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] ≠ ÷3
F_SEL[1:0] = ÷3
250
48
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
226.66
170
113.33
56.66
15
500
52
55
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
TABLE 5B. AC CHARACTERISTICS, V = V = 2.5V±5%, TA = 0°C TO 70°C
DD DDO
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f Output Frequency
OUT
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 2
212.5MHz, (637kHz - 10MHz)
0.65
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
159.375MHz, (637kHz - 10MHz)
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
0.61
0.74
0.64
187.5MHz, (637kHz - 10MHz)
0.80
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] ≠ ÷3
F_SEL[1:0] = ÷3
250
48
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
226.66
170
113.33
56.66
15
500
52
55
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
REVISION B 6/9/15
5 FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
5 Page 
POWER CONSIDERATIONS
844002 DATA SHEET
This section provides information on power dissipation and junction temperature for the 844002.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844002 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
• Power (core) = V * (I + I ) = 3.465V * (105mA + 12mA) = 405.4mW
MAX
DD_MAX
DD_MAX
DDA_MAX
• Power (outputs) = V * I = 3.465V * 120mA = 415.8mW
MAX
DDO_MAX DDO_MAX
Total Power = 405.4mW + 415.8mW = 821.2mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.821W * 66.6°C/W = 124.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the
type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION B 6/9/15
11 FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 844002.PDF ] | |
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