|
|
PDF 8T49N287 Data sheet ( Hoja de datos )
| Número de pieza | 8T49N287 | |
| Descripción | NG Octal Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 8T49N287 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
FemtoClock® NG Octal Universal
Frequency Translator
8T49N287
Datasheet
General Description
The 8T49N287 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency translation
application, including 1G, 10G, 40G and 100G Synchronous
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC
rates. The device may also behave as a frequency synthesizer.
The 8T49N287 accepts up to two differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. Each
PLL can use the other input for redundant backup of the primary
clock, but in this case, both input clocks must be related in frequency.
The device supports hitless reference switching between input clocks.
The device monitors all input clocks for Loss of Signal (LOS), and
generates an alarm when an input clock failure is detected. Automatic
and manual hitless reference switching options are supported. LOS
behavior can be set to support gapped or un-gapped clocks.
The 8T49N287 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conver-
sion, supporting all FEC rates, including the new revision of ITU-T
Recommendation G.709 (2009), most with 0ppm conversion error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• SyncE (G.8262) applications
• Wireless base station baseband
• Data communications
• 100G Ethernet
Features
• Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
• <0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz
• Operating modes: locked to input signal, holdover and free-run
• Initial holdover accuracy of ±50ppb
• Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
• Accepts frequencies ranging from 8kHz up to 875MHz
• Auto and manual input clock selection with hitless switching
• Clock input monitoring, including support for gapped clocks
• Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
• Operates from a 10MHz to 40MHz fundamental-mode crystal
• Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz (diff)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Four General Purpose I/O pins with optional support for status &
control:
• Four Output Enable control inputs may be mapped to any of the
eight outputs
• Lock, Holdover & Loss-of-Signal status outputs
• Open-drain Interrupt pin
• Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
• Optional Fast Lock function
• Programmable output phase delays in steps as small as 16ps
• Register programmable through I2C or via external I2C EEPROM
• Bypass clock paths for system tests
• Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
• -40°C to 85°C ambient operating temperature
• Package: 56QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016
1 page  
8T49N287 Datasheet
Number
41
38
35
32
53
52
18
19
Name
VCCO4
VCCO5
VCCO6
VCCO7
CAP0,
CAP0_REF
CAP1,
CAP1_REF
Type
Power
Power
Power
Power
Analog
Analog
Description
High-speed output supply voltage for output pair Q4, nQ4.
High-speed output supply voltage for output pair Q5, nQ5.
High-speed output supply voltage for output pair Q6, nQ6.
High-speed output supply voltage for output pair Q7, nQ7.
PLL0 External Capacitance.
PLL1 External Capacitance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%
Symbol
Parameter
Test Conditions
CIN
RPULLUP
Input Capacitance; NOTE 1
Internal
Pullup
Resistor
nRST,
SDATA, SCLK
nINT
GPIO[3:0]
RPULLDOWN
Internal Pulldown Resistor
LVCMOS;
Q[0:1], Q[4:7]
VCCOX = 3.465V
LVCMOS Q[2:3]
VCCOX = 3.465V
LVCMOS;
Q[0:1], Q[4:7]
VCCOX = 2.625V
Power
Dissipation
LVCMOS; Q[2:3]
VCCOX = 2.625V
CPD
Capacitance LVCMOS;
(per output Q[0:1], Q[4:7]
VCCOX = 1.89V
pair)
LVCMOS; Q[2:3]
VCCOX = 1.89V
LVDS, HCSL or
LVPECL;
Q[0:1], Q[4:7]
VCCOx = 3.465V or 2.625V
LVDS, HCSL or
LVPECL; Q[2:3]
VCCOx = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO [3:0]
LVCMOS;
Q[0:7], nQ[0:7]
Output HIGH
Output LOW
Minimum
NOTE: VCCOX denotes: VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE 1: This specification does not apply to OSCI and OSCO pins.
Typical
3.5
51
50
5.1
51
14.5
18.5
13
17.5
12.5
17
2
Maximum
4.5
5.1
25
20
Units
pF
k
k
k
k
pF
pF
pF
pF
pF
pF
pF
pF
k
©2016 Integrated Device Technology, Inc.
5
Revision 7, October 27, 2016
5 Page 
8T49N287 Datasheet
Device Start-up & Reset Behavior
The 8T49N287 has an internal power-up reset (POR) circuit and a
Master Reset input pin nRST. If either is asserted, the device will be
in the Reset State.
For highly programmable devices, it’s common practice to reset the
device immediately after the initial power-on sequence. IDT
recommends connecting the nRST input pin to a programmable logic
source for optimal functionality. It is recommended that a minimum
pulse width of 10ns be used to drive the nRST input pin.
While in the reset state (nRST input asserted or POR active), the
device will operate as follows:
• All registers will return to & be held in their default states as
indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as General-Purpose inputs.
• All clock outputs will be disabled.
• All interrupt status and Interrupt Enable bits will be cleared,
negating the nINT signal.
Upon the later of the internal POR circuit expiring or the nRST input
negating, the device will exit reset and begin self-configuration.
The device will load an initial block of its internal registers using the
configuration stored in the internal One-Time Programmable (OTP)
memory. Once this step is complete, the 8T49N287 will check the
register settings to see if it should load the remainder of its
configuration from an external I2C EEPROM at a defined address or
continue loading from OTP. See the section on I2C Boot Initialization
for details on how this is performed.
Once the full configuration has been loaded, the device will respond
to accesses on the serial port and will attempt to lock both PLLs to
the selected sources and begin operation. Once the PLLs are locked,
all the outputs derived from a given PLL will be synchronized and
output phase adjustments can then be applied if desired.
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave
in an I2C compatible configuration, to allow access any of the internal
registers for device programming or examination of internal status.
All registers are configured to have default values. See the specifics
for each register for details.
The device has the additional capability of becoming a master on the
I2C bus only for the purpose of reading its initial register
configurations from a serial EEPROM on the I2C bus. Writing of the
configuration to the serial EEPROM must be performed by another
device on the same I2C bus or pre-programmed into the device prior
to assembly.
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C
Specification for Normal and Fast mode operation. The device acts
as a slave device on the I2C bus at 100kHz or 400kHz using the
address defined in the Status Interface Control register (0006h), as
modified by the S_A0 input pin setting. The interface accepts
byte-oriented block write and block read operations. Two address
bytes specify the register address of the byte position of the first
register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k typical.
Current Read
S Dev Addr + R A Data 0 A Data 1 A
A Data n A P
Sequential Read
S
Dev Addr + W
A Offset Addr MSB A
Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n A P
Sequential Write
S Dev Addr + W A Offset Addr MSB A Offset Addr LSB A Data 0 A Data 1 A
A Data n A P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 3. I2C Slave Read and Write Cycle Sequencing
©2016 Integrated Device Technology, Inc.
11
Revision 7, October 27, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T49N287.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 8T49N281 | NG Octal Universal Frequency Translator | Integrated Device Technology |
| 8T49N282 | NG Octal Universal Frequency Translator | Integrated Device Technology |
| 8T49N283 | NG Octal Universal Frequency Translator |  IDT |
| 8T49N285 | NG Octal Universal Frequency Translator | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |