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Número de pieza | SR1 | |
Descripción | 4 pin Smart Reset | |
Fabricantes | STMicroelectronics | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SR1 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
No Preview Available ! UDFN6 (1.00 x 1.45 mm)
SR1
4 pin Smart Reset™
Datasheet - production data
Applications
Wearable
Activity tracker
Smartwatch
Smartglasses
Features
Operating voltage range 2 V to 5.5 V
Low supply current 1 µA
Integrated test mode
Single Smart Reset™ push-button input with
fixed extended reset setup delay (tSRC) from
0.5 s to 10 s in 0.5 s steps (typ.), option with
internal input pull-up resistor
Push-button controlled reset pulse duration
– Option 1: fully push-button controlled, no
fixed or minimum pulse width guaranteed
– Option 2: defined output reset pulse
duration (tREC), factory-programmed
Single reset output
– Active low or active high
– Push-pull or open drain with optional pull-
up resistor
Fixed Smart Reset input logic voltage levels
Operating temperature: -40 °C to +85 °C
UDFN6 package 1.00 mm x 1.45 mm
ECOPACK®2 (RoHS compliant, Halogen-
Free)
May 2014
This is information on a product in full production.
DocID026048 Rev 2
1/21
www.st.com
1 page SR1
2 Device overview
Device overview
Pin n°
1
2
3
4
5
6
Name
RST
VSS
SR
VCC
NC
NC
Table 1. Signal names
Type
Description
Output
Reset output, active low, open drain.
Supply ground Ground
Input
Smart Reset input, active low.
Supply voltage
-
-
Positive supply voltage for the device. A 0.1 µF decoupling
ceramic capacitor is recommended to be connected between
VCC and VSS pins.
Not connected (not bonded); should be connected to VSS.
Not connected (not bonded); should be connected to VSS.
Figure 3. SR1 block diagram
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DocID026048 Rev 2
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21
5 Page SR1
Typical operating characteristics
Figure 11. Test mode entry voltage (VTEST) vs. temperature (TA)
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Figure 12. Initial test mode time (tSRC-INI) vs. temperature (TA)
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DocID026048 Rev 2
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21
11 Page |
Páginas | Total 21 Páginas | |
PDF Descargar | [ Datasheet SR1.PDF ] |
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