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PDF uPD46184184B Data sheet ( Hoja de datos )
| Número de pieza | uPD46184184B | |
| Descripción | 18M-BIT DDR II SRAM 4-WORD BURST OPERATION | |
| Fabricantes | Renesas | |
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μPD46184184B
Datasheet
18M-BIT DDR II SRAM
4-WORD BURST OPERATION
R10DS0120EJ0200
Rev.2.00
Nov 09, 2012
Description
The μPD46184184B is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD46184184B integrate unique synchronous peripheral circuitry and a burst counter. All input
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage,
high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
• 1.8 ± 0.1 V power supply
• 165-pin PLASTIC BGA (13 x 15)
• HSTL interface
• PLL circuitry for wide output data valid window and future frequency scaling
• Pipelined double data rate operation
• Common data input/output bus
• Two-tick burst for low DDR transaction size
• Two input clocks (K and K#) for precise DDR timing at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
• Internally self-timed write control
• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
• User programmable impedance output (35 to 70 Ω)
• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
R10DS0120EJ0200 Rev.2.00
Nov 09, 2012
Page 1 of 32
1 page  
μPD46184184B
Symbol
CQ, CQ#
Type
Output
ZQ Input
DLL#
Input
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
Input
Input
Output
−
Supply
Supply
Supply
−
(2/2)
Description
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be
minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND
or left unconnected. The output impedance is adjusted every 20 μs upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the
new output impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to VDDQ through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function
is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to VDD.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the
input buffers.
Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC
Characteristics for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See Recommended DC Operating Conditions and DC Characteristics for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
R10DS0120EJ0200 Rev.2.00
Nov 09, 2012
Page 5 of 32
5 Page 
μPD46184184B
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Supply voltage
Output supply voltage
Input voltage
Input / Output voltage
Operating ambient temperature
Storage temperature
Symbol
VDD
VDDQ
VIN
VI/O
TA
Tstg
Conditions
(E** series)
(E**Y series)
Rating
−0.5 to +2.5
−0.5 to VDD
−0.5 to VDD+0.5 (2.5 V MAX.)
−0.5 to VDDQ+0.5 (2.5 V MAX.)
0 to 70
−40 to 85
−55 to +125
Unit
V
V
V
V
°C
°C
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Supply voltage
Output supply voltage
Input HIGH voltage
Input LOW voltage
Clock input voltage
Reference voltage
Symbol
VDD
VDDQ
VIH (DC)
VIL (DC)
VIN
VREF
Conditions
MIN.
1.7
1.4
VREF +0.1
−0.3
−0.3
0.68
TYP.
1.8
MAX. Unit Note
1.9 V
VDD V 1
VDDQ+0.3 V 1, 2
VREF −0.1 V 1, 2
VDDQ+0.3 V 1, 2
0.95 V
Notes 1. During normal operation, VDDQ must not exceed VDD.
2. Power-up: VIH ≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms
Recommended AC Operating Conditions (TA = 0 to 70°C, TA = −40 to 85°C)
Parameter
Input HIGH voltage
Input LOW voltage
Symbol
VIH (AC)
VIL (AC)
Conditions
MIN.
VREF +0.2
MAX.
VREF −0.2
Unit Note
V1
V1
Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V (2.5 V MAX.) for t ≤ TKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ TKHKH/2
Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).
R10DS0120EJ0200 Rev.2.00
Nov 09, 2012
Page 11 of 32
11 Page | ||
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