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uPD46185092B fiches techniques PDF

Renesas - 18M-BIT QDR II SRAM 2-WORD BURST OPERATION

Numéro de référence uPD46185092B
Description 18M-BIT QDR II SRAM 2-WORD BURST OPERATION
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uPD46185092B fiche technique
μPD46185092B
μPD46185182B
μPD46185362B
Datasheet
18M-BIT QDRTM II SRAM
2-WORD BURST OPERATION
R10DS0112EJ0200
Rev.2.00
Nov 09, 2012
Description
The μPD46185092B is a 2,097,152-word by 9-bit, the μPD46185182B is a 1,048,576-word by 18-bit and the
μPD46185362B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The μPD46185092B, μPD46185182B and μPD46185362B integrate unique synchronous peripheral circuitry and a
burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and
K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 3.3 ns (300 MHz), 2.0 ns (250 MHz)
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
R10DS0112EJ0200 Rev.2.00
Nov 09, 2012
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