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PDF L9352 Data sheet ( Hoja de datos )
| Número de pieza | L9352 | |
| Descripción | INTELLIGENT QUAD 2X5A/2X2.5A LOW-SIDE SWITCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L9352 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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L9352
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
s Quad low-side switch
s 2 x 5A designed as conventional switch
s 2 x 2.5A designed as switched current-regulator
s Low ON-resistance 4 x 0.2Ω (typ.)
s Power SO-36 - package with integrated
cooling area
s Integrated free-wheeling and clamping Z-diodes
s Output slope control
s Short circuit protection
s Selective overtemperature shutdown
s Open load detection
s Ground and supply loss detection
s External clock control
s Recirculation control
s Regulator drift detection
s Regulator error control
s Regulator resolution 5mA
s Status monitoring
s Status push-pull stages
s Electrostatic discharge (ESD) protection
Figure 1. Pin Connection
PowerSO-36
BARE DIE
ORDERING NUMBERS:
L9352
L9352-DIE1
DESCRIPTION
The L9352 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 250mA to 2.25A
and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
June 2002
99AT0060
GND
PGND3
PGND3
Q3
Q3
D3
D3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
PGND4
PGND4
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 CLK
35 ST3
34 IN1
33 IN3
32 ST1
31 PGND1
30 PGND1
29 VS
28 PGND2
27 PGND2
26 TEST
25 EN
24 ST2
23 IN4
22 IN2
21 ST4
20 VDD
19 VCC
1/21
1 page  
L9352
OPERATING RANGE
Symbol
Parameter
Test Conditions
VS
VCC, VDD
dVS/dt
VQ
VQ
Supply voltage
Supply voltage
Supply voltage transient time
Output voltage static
Output voltage induced by inductive switching Voltage will be
limited by internal
Z-diode clamping
VST Output voltage status
IST Output current status
Tj Junction temperature
Tjc Junction temperature during clamping
Σ = 30min
Σ = 15min
Min.
4.8
4.5
-1
-0.3
-0.3
-1
-40
Typ.
Max.
18
5.5
1
40
60
Unit
V
V
V/µs
V
V
6V
1 mA
150 °C
175 °C
190
.
ELECTRICAL CHARACTERISTCS:
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Power Supply
ISON Supply current
VS ≤ 18V
(outputs ON)
ISOFF Quiescent current
VS ≤ 18V
(outputs OFF)
Icc Supply current VCC (analog supply) VCC =5V
Idd Supply current VDD (digital supply) VDD =5V fCLK=0Hz
Idd Supply current VDD (digital supply) VDD =5V fCLK=250kHz
General Diagnostic Functions
VQU Open load voltage
VS ≥ 6.5V
(outputs OFF)
0.3
VthGND Signal-GND-loss threshold
VCC= 5V
0.1
VthPGL Power-GND-loss threshold
VCC= 5V
1.5
fCLK,min Clock frequency error
10
DCCLKe_l Clock duty cycle error detection low
ow
fCLK= 250 kHz
DCCLKe_ Clock duty cycle error detection high fCLK= 250 kHz
high
55
VSloss Supply detection
VCC = VDD = 5V
2
Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels)
IQU1,2 Open-load current channel 1, 2
VS ≥ 6.5V
50
IQO1,2 Over-load current channel 1, 2
VS ≥ 6.5V
5
Typ.
0.33
2.5
33,3
66,6
7.5
Max. Unit
5 mA
5 mA
5 mA
5 uA
5 mA
0.36 x VQ
1V
3.5 V
100 kHz
45 %
%
4.5 V
300 mA
9A
5/21
5 Page 
L9352
set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.
1.7 Drift Detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated for-
mula for the output current below shows the dependency of the load resistor to the output PWM. In this formula
the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The test-
mode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the
output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than ±14.3% of
the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with TD as other errors
IOUT = R-----L-V----+-B----RA-----TO-----N--- ⋅ PWM
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.
1.8 Other Test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indi-
cation of a proper logic functionality. The following table shows the functionality of this special test mode
EN
IN
TEST
OUT
STATUS
Note
1 XXX
X disable test mode
1 1 1 on
1 Drift mode
0X
off
test pattern
test condition one
0X
off
test pattern
test condition two
0X
off
test pattern
test condition three
00
off
test pattern
test condition four
01
on
test pattern
test condition four
For more details about the test condition four see timing diagram.
11/21
11 Page | ||
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| PDF Descargar | [ Datasheet L9352.PDF ] | |
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