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PDF M40SZ100W Data sheet ( Hoja de datos )
| Número de pieza | M40SZ100W | |
| Descripción | NVRAM supervisor | |
| Fabricantes | STMicroelectronics | |
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M40SZ100W
3 V NVRAM supervisor for LPSRAM
16
1
SO16
Features
Convert low power SRAMs into NVRAMs
3 V operating voltage
Precision power monitoring and power
switching circuitry
Automatic write-protection when VCC is out-of-
tolerance
Choice of supply voltage and power-fail
deselect voltage:
– VCC = 2.7 to 3.6 V; 2.55 V VPFD 2.70 V
Reset output (RST) for power on reset
1.25 V reference (for PFI/PFO)
Less than 15 ns chip enable access
propagation delay
Battery low pin (BL)
RoHS compliant
– Lead-free second level interconnect
Datasheet - production data
Description
The M40SZ100W NVRAM controller is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory. A
precision voltage reference and comparator
monitors the VCC input for an out-of-tolerance
condition.
When an invalid VCC condition occurs, the
conditioned chip enable output (ECON) is forced
inactive to write protect the stored data in the
SRAM. During a power failure, the SRAM is
switched from the VCC pin to the external battery
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write-protected until a valid power condition
returns.
December 2013
This is information on a product in full production.
DocID007528 Rev 4
1/20
www.st.com
1 page  
M40SZ100W
1 Device overview
Figure 1. Logic diagram
VCC VBAT
Device overview
E
PFI
RSTIN
M40SZ100W
VOUT
BL
ECON
PFO
RST
E
ECON
RST
RSTIN
BL
VOUT
VCC
VBAT
PFI
PFO
VSS
NC
VSS
Table 1. Signal names
Chip enable input
Conditioned chip enable output
Reset output (open drain)
Reset input
Battery low output (open drain)
Supply voltage output
Supply voltage
Backup supply voltage
Power fail input
Power fail output
Ground
Not connected internally
AI03933
DocID007528 Rev 4
5/20
20
5 Page 
M40SZ100W
Operation
2.2 Power-on reset output
All microprocessors have a reset input which forces them to a known state when starting.
The M40SZ100W has a reset output (RST) pin which is guaranteed to be low by VPFD (see
Table 7 on page 16). This signal is an open drain configuration. An appropriate pull-up
resistor to VCC should be chosen to control the rise time. This signal will be valid for all
voltage conditions, even when VCC equals VSS (with valid battery voltage).
Once VCC exceeds the power failure detect voltage VPFD, an internal timer keeps RST low
for tREC to allow the power supply to stabilize.
2.3 Reset input (RSTIN)
The M40SZ100W provides one independent input which can generate an output reset. The
duration and function of this reset is identical to a reset generated by a power cycle. Table 3
and Figure 7 illustrate the AC reset characteristics of this function. Pulses shorter than tRLRH
will not generate a reset condition. RSTIN is internally pulled up to VCC through a 100 k
resistor.
Figure 7. RSTIN timing waveform
2.4
RSTIN
tRLRH
RST (1)
tR1HRH
AI04768
1. With pull-up resistor
Table 3. Reset AC characteristics
Symbol
Parameter(1)
Min Max Unit
tRLRH(2)
tR1HRH(3)
RSTIN low to RSTIN high
RSTIN high to RST high
200 ns
40 200 ms
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 2.7 to 3.6 V (except where noted).
2. Pulse width less than 50 ns will result in no RESET (for noise immunity).
3. CL = 50 pF (see Figure 9 on page 15).
Battery low pin
The M40SZ100W automatically performs battery voltage monitoring upon power-up, and at
factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be
asserted if the battery voltage is found to be less than approximately 2.5 V. The BL pin will
remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up sequence or the next scheduled 24-hour
interval.
DocID007528 Rev 4
11/20
20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet M40SZ100W.PDF ] | |
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