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PDF ADF4355-2 Data sheet ( Hoja de datos )
| Número de pieza | ADF4355-2 | |
| Descripción | Microwave Wideband Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Microwave Wideband Synthesizer
with Integrated VCO
ADF4355-2
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 4400 MHz
The ADF4355-2 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
High resolution 38-bit modulus
when used with an external loop filter and an external reference
Low phase noise, VCO
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5 V typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
APPLICATIONS
frequency. A series of frequency dividers permits operation
from 54 MHz to 4400 MHz.
The ADF4355-2 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
3400 MHz to 6800 MHz. In addition, the VCO frequency is
connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow
the user to generate radio frequency (RF) output frequencies as
low as 54 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin and
software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
Wireless infrastructure (W-CDMA, TD-SCDMA,
The ADF4355-2 operates with analog and digital power supplies,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains
hardware and software power-down modes.
Clock generation
FUNCTIONAL BLOCK DIAGRAM
CE
AVDD
DVDD
VP
RSET
VVCO
VRF
AVDD
REFINA
REFIN B
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER
REG
FRACTION MODULUS
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
÷11/62/3/42//864
N COUNTER
AGND
CPGND
AGNDRF
Figure 1.
MULTIPLEXER
SDGND AGNDVCO
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
CREG1
CREG2
CPOUT
VTUNE
VREF
VBIAS
VREGVCO
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
ADF4355-2
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADF4355-2
Parameter
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Third
RF Output Power5
RF Output Power Variation
RF Output Power Variation (over
Frequency)
Level of Signal with RF Output
Disabled
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
Symbol Min
3400
53.125
KV
Normalized In-Band Phase Noise Floor
Fractional Channel6
Integer Channel7
Normalized 1/f Noise, PN1_f8
Integrated RMS Jitter
Spurious Signals due to Phase
Frequency Detector (PFD) Frequency
Typ
15
15
0.5
−27
−22
−20
−12
8
3
±1
±3
−60
−30
−116
−136
−138
−155
−113
−133
−135
−153
−110
−130
−132
−150
−221
−223
−116
150
−80
Max
6800
4400
Unit Test Conditions/Comments
MHz
MHz
MHz/V
MHz/V
MHz
Fundamental VCO range
Voltage standing wave ratio (VSWR) = 2:1
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
dBm
dBm
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTA+ = 1 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz to 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz, VCO = 4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz,
VCO = 4.4 GHz
VCO noise in open-loop conditions
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
10 kHz offset; normalized to 1 GHz
1 VCP is the voltage at the CPOUT pin.
2 IOL is the output low current.
3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
4 The value measured varies between 16, 20, 42, and 55, depending on the RF output stage power programmable level per Bit DB4 and DB5 in Register 6.
5 RF output power using the EV-ADF4355-2SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. The EV-ADF4355-2SD1Z RF
outputs are pulled up externally using a 7.4 nH inductor. Unused RF output pins are terminated in 50 Ω.
6 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
7 Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
8 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
Rev. B | Page 5 of 37
5 Page 
Data Sheet
–50 ÷1
÷2
–70
–90
–110
–130
–150
–170
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50 ÷1
÷2
–70
–90
–110
–130
–150
–170
1k
10k 100k
1M
10M
100M
FREQUENCY (Hz)
Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50
÷1
÷2
–70
–90
–110
–130
–150
–170
1k
10k 100k 1M
10M 100M
FREQUENCY (Hz)
Figure 12. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
ADF4355-2
10
9
8
7
–40°C
+25°C
+85°C
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (GHz)
Figure 13. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
0 SECOND HARMONIC
–5 THIRD HARMONIC
–10
–15
–20
–25
–30
–35
–40
–45
–50
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (GHz)
Figure 14. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
10
8
6
4
2
0
–2
–4
–6
–8
–10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
FREQUENCY (GHz)
Figure 15. RFOUTA+/RFOUTA− Power vs. Frequency (100 nH Inductors,
100 pF Bypass Capacitors, Board Measurement)
Rev. B | Page 11 of 37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADF4355-2.PDF ] | |
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