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Número de pieza | LTC6104 | |
Descripción | Bi-Directional Current Sense Amplifier | |
Fabricantes | Linear | |
Logotipo | ||
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No Preview Available ! FEATURES
■ Wide Supply Range: 4V to 60V with 70V Absolute
Maximum
■ Low Offset Voltage: ±450µV Maximum
■ Fast Response: 1µs Response Time
■ Gain Configurable with External Resistors; Each
Direction is Gain Configurable
■ Low Input Bias Current: 170nA Maximum
■ PSRR: 110dB Minimum
■ Output Current: ±1mA Maximum
■ Low Supply Current: 520µA, VS = 12V
■ Specified for –40°C to 125°C Temperature Range
■ Available in an 8-Lead MSOP Package
APPLICATIONS
■ Current Shunt Measurement
■ Battery Monitoring
■ Remote Sensing
■ Power Management
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC6104
High Voltage, High Side,
Bi-Directional Current
Sense Amplifier
DESCRIPTION
The LTC®6104 is a versatile, high voltage, high side, bi-
directional current sense amplifier. Design flexibility is
provided by the excellent device characteristics: ±450µV
maximum offset and only 520µA of current consumption
(typical at 12V). The LTC6104 operates on supplies from
4V to 60V.
The LTC6104 monitors bi-directional current via the voltage
across an external sense resistor (shunt resistor). This
sense voltage is then translated into a ground referenced
signal. Gain is set with three external resistors and can
be separately configured for both directions. Low DC
offset allows the use of a small shunt resistor and large
gain-setting resistors. As a result, power loss in the shunt
is minimal.
The wide operating supply range and high accuracy make
the LTC6104 ideal for a wide variety of automotive, industrial
and power management applications. A maximum input
sense voltage of 500mV allows a wide range of currents
to be monitored. The fast response makes the LTC6104
the perfect choice for load current warnings and shutoff
protection control. With very low supply current, the
LTC6104 is suitable for power sensitive applications.
The LTC6104 is available in an 8-lead MSOP package.
TYPICAL APPLICATION
TO
CHARGER/LOAD
16-Bit Resolution Bi-Directional Output into LTC1286 ADC
ILOAD
– VSENSE +
RSENSE
RIN RIN
100Ω 100Ω
+
12V
8
+INA
+–
A
VS
76
–INA –INB
5
+INB
–+
B
VS
VREF
LTC6104 OUT
1
CURRENT
MIRROR
ROUT
2.5k
V–
4
C2
0.1µF
R1 C1 +
2.3k 1µF 5V
VREF VCC
+IN
LTC1286
CS
CLK
–IN
LT®1004-2.5
GND
DOUT
6104 TA01a
TO µP
Step Response
VSENSE–
6V
∆VSENSE = 100mV
VOUT
1.5V IOUT = 100µA
1V
IOUT = 0µA
TA = 25°C
VS = 12V
RIN = 100Ω
VRSOEUNTS=E+5=k VS
VREF = 1V
TIME (1µs/DIV)
6104 G15
6104f
1
1 page TYPICAL PERFORMANCE CHARACTERISTICS
LTC6104
Step Response 0mV to 10mV
VS
VS –10mV
VSENSE–
2.5V
TA = 25°C
VS = 12V
RIN = 100Ω
RVSOEUNTS=E+5=k VS
VREF = 2V
2V VOUT
TIME (10µs/DIV)
6104 G11
Step Response 0mV to –10mV
VS + 10mV
VS
VSENSE–
2V
TA = 25°C
VS = 12V
RIN = 100Ω
VOUT
RVSOEUNTS=E+5=k VS
1.5V VREF = 2V
TIME (10µs/DIV)
6104 G12
Step Response –5mV to 5mV
VS + 5mV
VS – 5mV
VSENSE–
2.25V
2V
VOUT
1.75V
TA = 25°C
VS = 12V
RIN = 100Ω
VRSOEUNTS=E+5=k VS
VREF = 2V
TIME (10µs/DIV)
6104 G13
Step Response –50mV to 50mV
VS + 50mV
VS – 50mV VSENSE
6.5V
4V
CLOAD
1000pF
CLOAD
10pF
VOUT
1.5V
TA = 25°C
VS = 12V
RIN = 100Ω
RVSOEUNTS=E+5=k VS
VREF = 4V
TIME (10µs/DIV)
6104 G14
Step Response Rising Edge
VSENSE–
6V
∆VSENSE = 100mV
VOUT
1.5V IOUT = 100µA
1V
IOUT = 0µA
TA = 25°C
VS = 12V
RIN = 100Ω
RVSOEUNTS=E+5=k VS
VREF = 1V
TIME (1µs/DIV)
6104 G15
Step Response Rising Edge
VSENSE–
6V
5.5V
∆VSENSE– = 100mV
IOUT = 0µA
IOUT = –100µA
1V VOUT
0.5V
TA = 25°C
VS = 12V
RIN = 100Ω
RVSOEUNTS=E+5=k VS
VREF = 6V
TIME (1µs/DIV)
6104 G16
Step Response Rising Edge
VS + 50mV
VS – 50mV
7V
VSENSE–
Step Response Falling Edge
VSENSE–
6.5V
5V
VOUT
∆VSENSE– = 100mV
4.5V
VOUT
2V
TA = 25°C
VS = 12V
RIN = 100Ω
RVSOEUNTS=E+5=k VS
VREF = 4.5V
TIME (1µs/DIV)
6104 G17
TA = 25°C
VS = 12V
RIN = 100Ω
1.5V
1V
RVSOEUNTS=E+5=k VS
VREF = 1V
IOUT = 100µA
IOUT = 0µA
TIME (1µs/DIV)
6104 G18
6104f
5
5 Page LTC6104
APPLICATIONS INFORMATION
If the maximum output current, IOUT, is limited to 1mA,
ROUT equals 3V/1mA = 3k and RIN = 3k/6 – 0.3Ω (internal
device resistance) = 499.7Ω.
The output error due to DC offset is ±510µV (typ) and
the error due to offset current, IOS, is 3k • 100nA =
300µV(typ).
The maximum output error can therefore reach ±810µV
or 0.027% (–71dB) of the output full scale. Considering
the system input 60dB dynamic range (ISENSE = ±1mA to
±1A), the 71dB performance of the LTC6104 makes this
application feasible.
Output Error, EOUT, Due to the Current Mirror Errors,
IOUT-GAINERR and IOUT-OSERR
When VSENSE is negative, amplifier B would be on and
amplifier A off. The output of amplifier B drives an internal
current mirror which is connected to the OUT pin. This
current mirror has some error associated with it, and this
error can be calculated as follows:
IOUT-GAINERR = ±0.2% • IOUT, with IOUT = ±1mA,
IOUT-GAINERR(MAX) = ±2μA
IOUT-OSERR = ±0.2μA
IOUT-ERR(MAX) = IOUT-GAINERR + IOUT-OSERR = ±2μA +
±0.2μA = ±2.2μA
EOUT-ERR(MAX) = IOUT-ERR(MAX) • ROUT
The combined effect of amplifier offset and current mirror
errors is shown graphically in Figure 4.
100
RIN = 100Ω
ROUT = 5k
10
MAXIMUM
1
0.1 TYPICAL
0.01
–500
–300
–100 100
VSENSE (mV)
300 500
6104 F04
Figure 4. Output Error vs Input Voltage
Output Error, EOUT, Due to Trace Resistance
The LTC6104 uses the +INB pin for both the positive “B”
amplifier input and the positive supply input for both
amplifiers. If trace resistance (RT) become significant
(Figure 5), this supply current can cause an input offset
error, which can be calculated as follows:
EOUT(OFFSET)
=
RT
• IS
•
ROUT
RIN
Trace resistances to the –IN terminals will increase the
effective RIN value, causing a gain error (Figure 5). In ad-
dition, internal device resistance will add approximately
0.3Ω to RIN.
Gain error equals:
A V(ERROR)
=
RIN
ROUT
+ RT +
0.3Ω
–
ROUT
RIN
Minimizing resistance in the input traces is important and
care should be taken in the PCB layout. Make the trace
short and wide. Kelvin connection to the shunt resistor
pad should be used. Avoid tapping into this signal along
ILOAD
TO
CHARGER/LOAD
– VSENSE +
RSENSE
RIN RIN
+
RT
8
+INA
+–
A
VS
RT RT
RT
76
–INA –INB
5
+INB
–+
B
VS
IS
LTC6104 OUT
1
+
CURRENT
MIRROR
IOUT
VOUT
–
ROUT
+– VREF
V–
4
6104 F05
Figure 5. Errors from PCB Traces and Other Parasitic Resistances
6104f
11
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet LTC6104.PDF ] |
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