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PDF TS81102G0 Data sheet ( Hoja de datos )
| Número de pieza | TS81102G0 | |
| Descripción | Monolithic 10-bit high-speed (up to 2 GHz) demultiplexor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Programmable DMUX Ratio:
– 1:4: Data Rate Max = 1 Gsps
– PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output)
– 1:8: Data Rate Max = 2 Gsps
– PD (8b/10b) < 6/6.9 W (ECL 50Ω output)
– 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX
• Parallel Output Mode
• 8-/10-bit
• ECL Differential Input Data
• DataReady or DataReady/2 Input Clock
• Input Clock Sampling Delay Adjust
• Single-ended Output Data:
– Adjustable Common Mode and Swing
– Logic Threshold Reference Output
– (ECL, PECL, TTL)
• Asynchronous Reset
• Synchronous Reset
• ADC + DMUX Multi-channel Applications:
– Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment
• Differential Data Ready Output
• Built-in Self Test (BIST)
• Dual Power Supply VEE = -5V, VCC = +5V
• Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)
• TBGA 240 (Cavity Down) Package
DMUX 8-/10-bit
2 GHz 1:4/8
TS81102G0
Description
The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor,
designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed
ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B.
The TS81102G0 uses an innovative architecture, including a sampling delay adjust
and tunable output levels. It allows users to process the high-speed output data
stream down to processor speed and uses the very high-speed bipolar technology (25
GHz NPN cut-off frequency).
Rev. 2105C–BDC–11/03
1
1 page  
TS81102G0
Main Function
Description
Programmable
DMUX Ratio
The conversion ratio is programmable: 1:4 or 1:8.
Figure 3. Programmable DMUX Ratio
Input Words:
1,2,3,4,5,6,7,8,...
1:4
Output Words:
PortA
PortB
1 5 ...
26
PortC 3 7
PortD 4 8
PortE not used
PortF
not used
PortG not used
PortH not used
Input Words:
1,2,3,4,5,6,7,8,...
1:8
Output Words:
PortA
PortB
1 9 ...
2 10
PortC 3 11
PortD 4 12
PortE 5 13
PortF 6 14
PortG 7 15
PortH 8 16
Parallel Output
Mode
Figure 4. Parallel Mode
ClkIn
DR
PortA
PortB
PortC
PortD
PortE
PortF
PortG
PortH
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL)
The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to
ensure a proper phase between the clock and input data of the DMUX.
2105C–BDC–11/03
5
5 Page 
TS81102G0
Electrical
Operating
Characteristics
Tj (typical) = 70°C. Full Temperature Range: -40°C < Tc; Tj < 110°C.
(Guaranteed temperature range are depending on part number)
Table 4. Electrical Specifications
Parameter
Power Requirements
Positive supply voltage
Negative supply voltage
Supply Currents
ECL (50Ω) and PECL (50Ω)
VCC (for every configuration)
1:8, 8 bits
1:8, 10 bits
1:4, 8 bits
1:4, 10 bits
TTL (75Ω)
VCC (for every configuration)
1:8, 8 bits
1:8, 10 bits
1:4, 8 bits
1:4, 10 bits
Nominal power dissipation
ECL (50Ω)
1:8, 8 bits
1:8, 10 bits
1:4, 8 bits
1:4, 10 bits
Symbol
VCC
VPLUSDOUT
ECL
PECL
TTL
VEE
VCC
–
VPLUSD
VPLUSD
VPLUSD
VEE
ICC
IPLUSD
IEE
IPLUSD
IEE
IPLUSD
IEE
IPLUSD
IEE
ICC
IPLUSD
IEE
IPLUSD
IEE
IPLUSD
IEE
IPLUSD
IEE
PD
PD
PD
PD
Test
Level
Min
Value
Typ
Max
4.75 5 5.25
–––
1 -0.25 0 0.25
3.135 3.3 3.465
3.135 3.3 3.465
1 -5.25 -5 -4.75
– 31 –
540
1180
1820
– 719 –
640
1140
2240
1 – 790 –
270 590 910
– 592 –
320 720 1120
– 634 –
– 31 –
760
1610
2440
– 872 –
900
1770
3010
1 – 980 –
380 810 1220
– 670 –
450 880 1510
– 729 –
5.2 5.6
6
5.9 6.4 6.9
1
3.9 4.1 4.3
4.2 4.5 4.7
Unit Note
V
–
V
V
V
V
(1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
(1)
W
W
W
W
2105C–BDC–11/03
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TS81102G0.PDF ] | |
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