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PDF STF21N90K5 Data sheet ( Hoja de datos )

Número de pieza STF21N90K5
Descripción N-CHANNEL MOSFET
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! STF21N90K5 Hoja de datos, Descripción, Manual

STB21N90K5, STF21N90K5, STP21N90K5,
STW21N90K5
N-channel 900 V, 0.25 Ω typ., 18.5 A Zener-protected SuperMESH™ 5
Power MOSFET in a D2PAK, TO-220FP, TO-220 and TO-247 packages
Datasheet — production data
Features
Order codes VDSS RDS(on)max ID
PW
STB21N90K5
250 W
STF21N90K5
900 V
STP21N90K5
STW21N90K5
40 W
< 0.299 Ω 18.5 A
250 W
TO-220 worldwide best RDS(on)
Worldwide best FOM (figure of merit)
Ultra low gate charge
100% avalanche tested
Zener-protected
Applications
Switching applications
TAB
3
1
D2PAK
TAB
3
2
1
TO-220FP
3
2
1
TO-220
3
2
1
TO-247
Figure 1. Internal schematic diagram
D(2, TAB)
Description
These devices are N-channel Power MOSFETs
developed using SuperMESH™ 5 technology.
This revolutionary, avalanche-rugged, high
voltage Power MOSFET technology is based on
an innovative proprietary vertical structure. The
result is a drastic reduction in on-resistance and
ultra low gate charge for applications which
require superior power density and high
efficiency.
G(1)
S(3)
AM01476v1
Table 1. Device summary
Order codes
STB21N90K5
STF21N90K5
STP21N90K5
STW21N90K5
Marking
21N90K5
Package
D2PAK
TO-220FP
TO-220
TO-247
Packaging
Tape and reel
Tube
October 2012
This is information on a product in full production.
Doc ID 16744 Rev 6
1/22
www.st.com
22

1 page




STF21N90K5 pdf
STB21N90K5, STF21N90K5, STP21N90K5, STW21N90K5
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min. Typ. Max. Unit
17 ns
VDD = 720 V, ID = 10 A,
RG=4.7 Ω, VGS=10 V
(see Figure 22)
-
27
52
-
ns
ns
40 ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
ISD
ISDM
VSD(1)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD= 18.5 A, VGS=0
-
-
19 A
76 A
1.5 V
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 18.5 A, VDD= 60 V
548
di/dt = 100 A/µs,
- 12
(see Figure 21)
46
ns
μC
A
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 18.5 A,VDD= 60 V
di/dt=100 A/µs,
Tj=150 °C
(see Figure 21)
660
- 15
45
ns
μC
A
1. Pulsed: pulse duration = 300µs, duty cycle 1.5%
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
V(BR)GSO Gate-source breakdown voltage IGS = ±1 mA, ID = 0
Min. Typ. Max. Unit
30 - - V
The built-in-back Zener diodes have specifically been designed to enhance not only the
device’s ESD capability, but also to make them safely absorb possible voltage transients that
may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 16744 Rev 6
5/22

5 Page





STF21N90K5 arduino
STB21N90K5, STF21N90K5, STP21N90K5, STW21N90K5
Table 9. D²PAK (TO-263) mechanical data
Dim.
A
A1
b
b2
c
c2
D
D1
E
E1
e
e1
H
J1
L
L1
L2
R
V2
Min.
4.40
0.03
0.70
1.14
0.45
1.23
8.95
7.50
10
8.50
4.88
15
2.49
2.29
1.27
1.30
mm
Typ.
2.54
0.4
Package mechanical data
Max.
4.60
0.23
0.93
1.70
0.60
1.36
9.35
10.40
5.28
15.85
2.69
2.79
1.40
1.75
Doc ID 16744 Rev 6
11/22

11 Page







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