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PDF HMC1122 Data sheet ( Hoja de datos )
| Número de pieza | HMC1122 | |
| Descripción | Silicon Digital Attenuator | |
| Fabricantes | Analog Devices | |
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Data Sheet
0.1 GHz to 6.0 GHz, 0.5 dB LSB, 6-Bit,
Silicon Digital Attenuator
HMC1122
FEATURES
Attenuation range: 0.5 dB LSB steps to 31.5 dB
Low insertion loss
1.1 dB at 1 GHz
1.3 dB at 2 GHz
Typical step error: less than ±0.1 dB
Excellent attenuation accuracy
Safe state transitions
High linearity
Input 0.1dB compression (P0.1dB): 30 dBm typical
Input third-order intercept (IP3): 55 dBm typical
RF settling time (0.05 dB final RF output): 250 ns
Low phase shift error: 6° at 1 GHz
Single supply operation: 3.3 V to 5 V
ESD rating: Class 2 (2 kV HBM)
24-lead, 4 mm × 4 mm LFCSP package: 16 mm2
Pin compatible to the HMC624A
APPLICATIONS
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
IF and RF designs
FUNCTIONAL BLOCK DIAGRAM
24 23 22 21 20 19
P/S 1
18 VDD
CLK 2
SERIN 3
SERIAL/
PARALLEL
INTERFACE
17 PUP1
16 PUP2
LE 4
GND 5
ATTIN 6
7
6-BIT/
DIGITAL
ATTENUATOR
15 SEROUT
14 GND
13 ATTOUT
8 9 10 11 12
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The HMC1122 is a 6-bit digital attenuator operating from
0.1 GHz to 6 GHz with a 31.5 dB attenuation control range in
0.5 dB steps.
The HMC1122 is implemented in a silicon process, offering
very fast settling time, low power consumption, and high ESD
robustness. The device features safe state transitions and
optimized for excellent step accuracy and high linearity over
frequency and temperature range. The RF input and output are
internally matched to 50 Ω and do not require any external
matching components. The design is bidirectional; therefore,
the RF input and output are interchangeable.
The HMC1122 operates on a single supply ranging from 3.3 V
to 5 V with no performance change due to an on-chip regulator.
The device incorporates a driver that provides both serial and
parallel control of the attenuator. The device also features a user-
selectable power-up state and a serial output port for cascading
other serial controlled components.
The HMC1122 comes in a RoHS compliant, compact, 4 mm ×
4 mm LFCSP package, and is pin compatible to the HMC624A.
A fully populated evaluation board is available.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
RF Input Power, PIN (TCASE = 85°C)
Supply Voltage
Digital Control Input Voltage
Continuous Power Dissipation, PDISS
Junction to Case Thermal Resistance, θJC
(at Maximum Power Dissipation)
Temperature
Junction, TJ
Storage
Reflow
ESD Sensitivity
Human Body Model (HBM)
Rating
25 dBm
−0.3 V to +5.5 V
−0.3 V to VDD + 0.5 V
0.31 W
156°C/W
135°C
−65°C to +150°C
260°C (MSL3 Rating)
2 kV (Class 2)
HMC1122
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
ESD CAUTION
Rev. 0 | Page 5 of 15
5 Page 
Data Sheet
HMC1122
P/S X
MSB
[FIRST IN]
tCS tCH
MSB
[FIRST IN]
SERIN X
D5
D4
D3
D2
D1
D0
X
tLN tLEW
CLK
tSCK
LE
Figure 26. Serial Mode Timing Diagram
Table 6. Timing Specifications
Parameter
Description
tSCK Minimum serial period, see Figure 26
tCS Control setup time, see Figure 26
tCH Control hold time, see Figure 26
tLN LE setup time, see Figure 26
tLEW Minimum LE pulse width, see Figure 26 and Figure 27
tLES Minimum LE pulse spacing, see Figure 26
tCKN Serial clock hold time from LE, see Figure 26
tPH Hold time, see Figure 27
tPS Setup time, see Figure 27
Min
70
15
15
D[5:0]
NEXT WORD
tCKN
tLES
Typ
20
10
630
0
10
2
X
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARALLEL MODE INTERFACE
The HMC1122 has six digital control inputs, D0 (LSB) to D5
(MSB), to select the desired attenuation state in parallel mode, as
shown in Table 5. The parallel control interface is activated when
P/S is set to low. In parallel mode operation, the parallel control
inputs (D0 to D5) must always be kept at a valid logic level (VIH or
VIL). It is recommended to use pull-down resistors on all parallel
control input lines if the device driving them goes to a high
impedance state during hibernation.
There are two modes of parallel operation: direct parallel and
latched parallel.
Direct Parallel Mode
The LE pin must be kept high. The attenuation state is changed
by the control voltage inputs (D0 to D5) directly. This mode is
ideal for manual control of the attenuator.
Latched Parallel Mode
The LE pin must be kept low when changing the control voltage
inputs (D0 to D5) to set the attenuation state. When the desired
state is set, LE must be toggled high to transfer the 6-bit data to
the bypass switches of the attenuator array, and then toggled
low to latch the change into the device until the next desired
attenuation change (see Figure 27 in conjunction with Table 6).
P/S X
D5 TO D0
X
tPS tPH
D[5:0]
PARALLE L
CONTROL
tLEW
X
LE
Figure 27. Latched Parallel Mode Timing Diagram
POWER-UP INTERFACE
The HMC1122 uses the PUP1 and PUP2 control voltage inputs
to set the attenuation value to a known value at power-up before
the initial control data word is provided in either serial or parallel
mode. When the attenuator powers up with LE = low, the state
of PUP1 and PUP2 determines the power-up state of the device
per the truth table shown in Table 7. The attenuator latches in
the desired power-up state approximately 200 ms after power-up.
Table 7. PUPx Truth Table1
Attenuation State
LE
31.5 dB
Low
24.0 dB
Low
16.0 dB
Low
0 dB (Reference)
Low
Determined by D0 to D5
High
PUP1
Low
High
Low
High
Don’t care
PUP2
Low
Low
High
High
Don’t care
1 The PUPx pins must always be kept at a valid logic level (VIH or VIL) and not be
left floating.
Rev. 0 | Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HMC1122.PDF ] | |
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