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PDF CY7S1049GE Data sheet ( Hoja de datos )
| Número de pieza | CY7S1049GE | |
| Descripción | 4-Mbit (512K words x 8 bit) Static RAM | |
| Fabricantes | Cypress | |
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CY7S1049G
CY7S1049GE
4-Mbit (512K words × 8 bit) Static RAM
with PowerSnooze™ and Error Correcting Code (ECC)
4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■ High speed
❐ Access time (tAA) = 10 ns / 15 ns
■ Ultra-low power Deep-Sleep (DS) current
❐ IDS = 15 µA
■ Low active and standby currents
❐ Active Current ICC = 38-mA typical
❐ Standby Current ISB2 = 6-mA typical
■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■ Embedded ECC for single-bit error correction
■ Error indication (ERR) pin to indicate 1-bit error detection and
correction
■ 1.0-V data retention
■ TTL- compatible inputs and outputs
■ Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)
molded SOJ
Functional Description
The CY7S1049G/CY7S1049GE is a high-performance
PowerSnooze™ static RAM organized as 512K words × 8 bits.
This device features fast access times (10 ns) and a unique
ultra-low power Deep-Sleep mode. With Deep-Sleep mode
currents as low as 15 µA, the CY7S1049G/CY7S1049GE
devices combine the best features of fast and low- power SRAMs
in industry-standard package options. The device also features
embedded ECC. logic which can detect and correct single-bit
errors in the accessed location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O7) and address pins (A0
through A18) respectively.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O7).
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1049G is available in 44-pin TSOP II, and 36-pin
Molded SOJ (400 Mils).
Product Portfolio
Product [1]
Range
CY7S1049G(E)18
CY7S1049G(E)30
CY7S1049G(E)
Industrial
VCC Range (V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5–5.5 V
Speed
(ns)
15
10
10
Power Dissipation
Operating
(mA)
ICC,
f = fmax
Typ [2] Max
Standby,
(mA)
ISB2
Typ [2] Max
Deep-Sleep
current (µA)
Typ [2] Max
– 40 6 8 – 15
38 45
38 45
Notes
1. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
2.
Typical values are included for reference only and are not guaranteed
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5
or tested.
V–5.5 V),
Typical values
TA = 25 °C.
are
measured
at
VCC
=
1.8
V
(for
VCC
range
of
1.65
V–2.2
V),
VCC
=
3
V
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-95414 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2016
1 page  
Pin Configurations (continued)
Figure 3. 36-pin SOJ pinout without ERR [5]
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SOJ
36 DS
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
Figure 4. 36-pin SOJ pinout with ERR [5, 6]
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SOJ
36 DS
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 ERR
CY7S1049G
CY7S1049GE
Notes
5. NC pins are not connected internally to the die.
6. ERR is an output pin.
Document Number: 001-95414 Rev. *C
Page 5 of 21
5 Page 
AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
Parameter [18]
Description
Read Cycle
tRC Read cycle time
tAA Address to data valid
tOHA
Data hold from address change
tACE CE LOW to data valid
tDOE
OE LOW to data valid
tLZOE
OE LOW to low impedance [19, 20, 21]
tHZOE
OE HIGH to HI-Z [19, 20, 21]
tLZCE
CE LOW to low impedance [19, 20, 21]
tHZCE
CE HIGH to HI-Z [19, 20, 21]
tPU CE LOW to power-up [21]
tPD CE HIGH to power-down [21]
Write Cycle [22, 23]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to low impedance [19, 20, 21]
WE LOW to HI-Z [19, 20, 21]
CY7S1049G
CY7S1049GE
10 ns
Min Max
10 –
– 10
3–
– 10
– 4.5
0–
–5
3–
–5
0–
– 10
10 –
7–
7–
0–
0–
7–
5–
0–
3–
–5
15 ns
Min Max
Unit
15 – ns
– 15 ns
3 – ns
– 15 ns
– 8 ns
0 – ns
– 8 ns
3 – ns
– 8 ns
0 – ns
– 15 ns
15 – ns
12 – ns
12 – ns
0 – ns
0 – ns
12 – ns
8 – ns
0 – ns
3 – ns
– 8 ns
Notes
18.
Test conditions assume a signal transition time
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for
(rise/fall) of
VCC < 3 V).
3 ns or less, timing
Test conditions for the
reference levels of
read cycle use output
l1o.a5diVng(fsohroVwCnCin>pa3rtV(a))aonf FdigVuCreC/52o(nfopraVgeC8C,
< 3 V), and input pulse
unless specified otherwise.
19. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage.
20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
21. These parameters are guaranteed by design.
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
23. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be the sum of tHZWE and tSD.
Document Number: 001-95414 Rev. *C
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY7S1049GE.PDF ] | |
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