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PDF SST25WF020 Data sheet ( Hoja de datos )
| Número de pieza | SST25WF020 | |
| Descripción | 1.8V SPI Serial Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Obsolete Device
Please contact Microchip Sales for replacement information.
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 are members of
the Serial Flash 25 Series family and feature a four-wire, SPI-compatible interface
that allows for a low pin-count package which occupies less board space and ulti-
mately lowers total system costs. SPI serial flash memory is manufactured with
SST proprietary, high performance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 40MHz
• Superior Reliability
– Endurance: 100,000 Cycles
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 20MHz)
– Standby Current: 2 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
(2 Mbit and 4 Mbit only)
• Fast Erase and Byte-Program:
– Chip-Erase Time: 125 ms (typical)
– Sector-/Block-Erase Time: 62ms (typical)
– Byte-Program Time: 50 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-contact WSON (5mm x 6mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005016C
11/14
1 page  
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Memory Organization
EOL Data Sheet
The SST25WF512/010/020/040 SuperFlash memory arrays are organized in uniform 4 KByte with 16
KByte, 32 KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay erasable blocks.
Device Operation
The SST25WF512/010/020/040 are accessed through the SPI (Serial Peripheral Interface) bus com-
patible protocol. The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the
device, and data is accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK).
The SST25WF512/010/020/040 support both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations.
The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the
bus master is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising
edge of the SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the
SCK clock signal.
CE#
MODE 3
SCK MODE 0
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Figure 3: SPI Protocol
1328 F03.0
©2014 Silicon Storage Technology, Inc.
5
DS20005016C
11/14
5 Page 
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
EOL Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020/
040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The
Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The
complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-to-
low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signifi-
cant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 9: Device Operation Instructions for SST25WF512 and SST25WF010
Instruction
Read
High-Speed Read
4 KByte Sector-
Erase3
32 KByte Block-
Erase4
Chip-Erase
Byte-Program
AAI-Word-Pro-
gram5
RDSR6
EWSR7
WRSR
WREN7
WRDI
RDID8
EBSY
DBSY
JEDEC-ID
EHLD
Description
Op Code Cycle1
Read Memory
0000 0011b (03H)
Read Memory at Higher 0000 1011b (0BH)
Speed
Erase 4 KByte of
memory array
0010 0000b (20H)
Erase 32 KByte block
of memory array
0101 0010b (52H)
Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
To Program One Data Byte 0000 0010b (02H)
Auto Address Increment 1010 1101b (ADH)
Programming
Read-Status-Register 0000 0101b (05H)
Enable-Write-Status-
Register
0110 0000b (50H)
Write-Status-Register 0000 0001b (01H)
Write-Enable
0000 0110b (06H)
Write-Disable
0000 0100b (04H)
Read-ID
1001 0000b (90H)
or
1010 1011b (ABH)
Enable SO to output RY/ 0111 0000b (70H)
BY# status during AAI
programming
Disable SO to output RY/ 1000 0000b (80H)
BY# status during AAI
programming
JEDEC ID read
1001 1111b (9FH)
Enable HOLD# pin func-
tionality of the RST#/
HOLD# pin
1010 1010b (AAH)
Address
Cycle(s)2
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
0
Dummy
Cycle(s)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data
Cycle(s)
1 to
1 to
Maximum
Frequency
20 MHz
0
0
0
1
2 to
1 to
0
1
0
0
1 to
40 MHz
0
0
3 to
0
T9.0 20005016
©2014 Silicon Storage Technology, Inc.
11
DS20005016C
11/14
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25WF020.PDF ] | |
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