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PDF SST25WF020A Data sheet ( Hoja de datos )
| Número de pieza | SST25WF020A | |
| Descripción | 2 Mbit 1.8V SPI Serial Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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SST25WF020A
2 Mbit 1.8V SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 40MHz
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read Current: 4 mA (typical)
- Standby Current: 10 μA (typical)
- Power-down Mode Standby Current: 4 μA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 64 KByte overlay blocks
• Page Program Mode
- 256 Bytes/Page
• Fast Erase and Page-Program:
- Chip-Erase Time: 300 ms (typical)
- Sector-Erase Time: 40 ms (typical)
- Block-Erase Time: 80 ms (typical)
- Page-Program Time: 3 ms/ 256 bytes (typical)
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without deselect-
ing the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of
the status register
• Software Write Protection
- Write protection through Block-Protection bits
in status register
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact USON (2mm x 3mm)
- 8-contact WDFN(5mm x 6mm)
• All devices are RoHS compliant
Product Description
SST25WF020A is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 1.65-1.95V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST25WF020A is offered in 8-lead SOIC, 8-contact
USON, and 8-contact WDFN packages. See Figure 2-
1 for the pin assignments.
2014 Microchip Technology Inc.
DS20005139E-page 1
1 page  
SST25WF020A
3.0 MEMORY ORGANIZATION
The SST25WF020A SuperFlash memory arrays are
organized in 64 uniform 4 KByte sectors, with four
64 KByte overlay erasable blocks.
FIGURE 3-1:
MEMORY MAP
Number of 64 KByte
Blocks
3
Number of Sectors Top of Memory Block
63
03FFFFH
03F000H
48
030FFFH
030000H
31
01FFFFH
01F000H
1
01FFFFH
16 010000H
15
00FFFFH
00F000H
0
1
001FFFH
001000H
0
000FFFH
000000H
Bottom of Memory Block
25139 F51.0
4.0 DEVICE OPERATION
SST25WF020A is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25WF020A supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1:
CE#
MODE 3
SCK MODE 0
SPI PROTOCOL
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
2513 F03.0
2014 Microchip Technology Inc.
DS20005139E-page 5
5 Page 
SST25WF020A
5.3 Page-Program
The Page-Program instruction programs up to 256
Bytes of data in the memory. The data for the selected
page address must be in the erased state (FFH) before
initiating the Page-Program operation. A Page-Pro-
gram applied to a protected memory area will be
ignored. Prior to the program operation, execute the
WREN instruction.
To execute a Page-Program operation, the host drives
CE# low, then sends the Page-Program command
cycle (02H), three address cycles, followed by the data
to be programmed, and then drives CE# high. The pro-
grammed data must be between 1 to 256 Bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored. Poll the BUSY bit
in the Status register, or wait TPP, for the completion of
FIGURE 5-3:
PAGE-PROGRAM SEQUENCE
the internal, self-timed, Page-Program operation. See
Figure 5-3 for the Page-Program sequence and Figure
6-9 for the Page-Program flow chart.
When executing Page-Program, the memory range for
the SST25WF020A is divided into 256-Byte page
boundaries. The device handles the shifting of more
than 256 Bytes of data by maintaining the last 256
Bytes as the correct data to be programmed. If the tar-
get address for the Page-Program instruction is not the
beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be pro-
grammed at the start of that target page.
CE#
SCK
MODE 3
MODE 0
0 1 2345 6 78
15 16
23 24 31 32
39
SI
SO
CE#(cont’)
MSB
02
ADD.
LSB MSB
ADD.
HIGH IMPEDANCE
ADD. Data Byte 0
LSB MSB LSB
SCK(cont’)
SI(cont’)
SO(cont’)
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
MSB
Data Byte 1
LSB MSB
Data Byte 2
Data Byte 255
LSB MSB
LSB
HIGH IMPEDANCE
25139 F60.1
2014 Microchip Technology Inc.
DS20005139E-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25WF020A.PDF ] | |
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