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PDF MWS5101 Data sheet ( Hoja de datos )
| Número de pieza | MWS5101 | |
| Descripción | 256-Word by 4-Bit LSI Static Random-Access Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101
A3
A2
AI
AD
A5
AS
A7
VSS
OJ: I
001
012
I 22
2 21
~ 20
4 19
5 18
S 17
7 16
8 15
9 14
10 13
II 12
TOP VIEW
vOO
A4
rRlnW
QO
CS2
004
OI4
003
OI3
DO~
92CS-29976RI
TI;RMINAL ASSIGNMENT
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard pinout
• Output-Disable for common I/O systems
• Very low operating current-8 mA • 3-state data output for bus-oriented
= =at Voo 5 V and cycle time 1 ps
systems
• Two Chip-Select inputs-simple
• Separate data inputs and outputs
memory expansion
• Memory retention for standby battery
voltage of 2 V min
The RCA-MWS5101 is a 256-word by 4-bit static random-
access memory designed for use In memory systems where
high speed, very low operating current, and simplicity in
use are desirable. It has separate data inputs and outputs
and utilizes a single power supply of 4 to 6.5 volts.
Two Chir·Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high-impedance state
during a write operation independent of the Chip-Select
input condition. The output assumes a high-impedance
state when the Output Disable is at high level or when the
chip is deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5-V
operation, excellent system noise margin is preserved by
using an external pull-up resistor at each input.
For Rpplications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, RCA-CDP1822, may be used
The MWS5101 types are supplied in 22-lead hermetic dual-
in-line, side-brazed ceramic packages (0 suffix), in 22-lead
dual-in-line plastic packages (E suffix), and in chip form (H
suffix).
OPERATIONAL MODES
MODE
READ
WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
CIiTP Select 1
CS1
0
0
0
1
X
X
INPUTS
Chip Select 2 Output Disable
CS2 00
10
10
11
XX
0X
X1
Logic 1 = High
Logic 0 = Low
X = Don't Care
Read/Write
R/VI
1
0
0
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
I
File Number 1106
686 ___________________________________________________________
1 page  
Random-AccessMemories(RAM~ _________________________________________
MWS5101
DATA RETENTION CHARACTERISTICS at TA = 0 to 70· C; See Fig. 3
TEST CONDITIONS
LIMITS
CHARACTE RISTIC
V(DVRi
VDD
(V)
All Types
Min. Typ.-
Minimum Data
Retention Voltage. VDR - - - 1.5
Data Retention
QUiescent
Current. 100
L2 Types
L3 Types
2
-
-
-
2
5
Chip Deselect to Data
Retention Time.
Recovery to Normal
Operation Time.
tCDR
tRC
VDD to VDR Rise and
Fall Time
tr.tf
-
-
2
5 600 -
5 600 -
5 1-
- Typical values are for T A = 25°C and nominal VOO
Max.
2
10
50
-
-
-
UNITS
V
jJA
ns
JJS
VDD
rtfICDR
VDR
CS2
ViHV,\L1X_,-___________--J
92CS-30B05RI
Fig. 3 - Low Vee data retention timing waveforms.
WRITE
ADDRESS
DECODER
READ
ADDRESS
DECODER
5
o
i«o'!
Voo
9ZCS-27256R2
Fig. 4 - Memory cell configuration
690 _______________________________________________________________
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MWS5101.PDF ] | |
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